From 4587406d44c589c4cdeccd40512f0c285f42f38b Mon Sep 17 00:00:00 2001
From: Astro <astro@spaceboyz.net>
Date: Tue, 17 Sep 2019 00:13:46 +0200
Subject: [PATCH] ad7172: setup adc

---
 firmware/src/ad7172/adc.rs  | 19 ++++++++++++++++++-
 firmware/src/ad7172/mod.rs  |  4 ++++
 firmware/src/ad7172/regs.rs |  5 +++++
 firmware/src/main.rs        |  1 +
 4 files changed, 28 insertions(+), 1 deletion(-)

diff --git a/firmware/src/ad7172/adc.rs b/firmware/src/ad7172/adc.rs
index 96672bd..cd3dc7d 100644
--- a/firmware/src/ad7172/adc.rs
+++ b/firmware/src/ad7172/adc.rs
@@ -2,7 +2,10 @@ use embedded_hal::digital::v2::OutputPin;
 use embedded_hal::blocking::spi::Transfer;
 use super::checksum::{ChecksumMode, Checksum};
 use super::AdcError;
-use super::{regs, regs::RegisterData, Input};
+use super::{
+    regs, regs::RegisterData,
+    Input, RefSource, PostFilter, DigitalFilterOrder,
+};
 
 /// AD7172-2 implementation
 ///
@@ -41,13 +44,27 @@ impl<SPI: Transfer<u8>, NSS: OutputPin> Adc<SPI, NSS> {
         Ok(())
     }
 
+    pub fn set_sync_enable(&mut self, enable: bool) -> Result<(), AdcError<SPI::Error>> {
+        self.update_reg(&regs::GpioCon, |data| {
+            data.set_sync_en(enable);
+        })
+    }
+
     pub fn setup_channel(
         &mut self, index: u8, in_pos: Input, in_neg: Input
     ) -> Result<(), AdcError<SPI::Error>> {
         self.update_reg(&regs::SetupCon { index }, |data| {
             data.set_bipolar(false);
+            data.set_refbuf_pos(true);
+            data.set_refbuf_neg(true);
+            data.set_ainbuf_pos(true);
+            data.set_ainbuf_neg(true);
+            data.set_ref_sel(RefSource::External);
         })?;
         self.update_reg(&regs::FiltCon { index }, |data| {
+            data.set_enh_filt_en(true);
+            data.set_enh_filt(PostFilter::F16SPS);
+            data.set_order(DigitalFilterOrder::Sinc5Sinc1);
             // 10 Hz data rate
             data.set_odr(0b10011);
         })?;
diff --git a/firmware/src/ad7172/mod.rs b/firmware/src/ad7172/mod.rs
index 59ae29e..7543d17 100644
--- a/firmware/src/ad7172/mod.rs
+++ b/firmware/src/ad7172/mod.rs
@@ -113,9 +113,13 @@ impl fmt::Display for RefSource {
 
 #[repr(u8)]
 pub enum PostFilter {
+    /// 27 SPS, 47 dB rejection, 36.7 ms settling
     F27SPS = 0b010,
+    /// 21.25 SPS, 62 dB rejection, 40 ms settling
     F21SPS = 0b011,
+    /// 20 SPS, 86 dB rejection, 50 ms settling
     F20SPS = 0b101,
+    /// 16.67 SPS, 92 dB rejection, 60 ms settling
     F16SPS = 0b110,
     Invalid = 0b111,
 }
diff --git a/firmware/src/ad7172/regs.rs b/firmware/src/ad7172/regs.rs
index 24bd069..d00b900 100644
--- a/firmware/src/ad7172/regs.rs
+++ b/firmware/src/ad7172/regs.rs
@@ -152,6 +152,11 @@ impl data::Data {
     }
 }
 
+def_reg!(GpioCon, gpio_con, 0x06, 2);
+impl gpio_con::Data {
+    reg_bit!(sync_en, set_sync_en, 0, 3, "Enables the SYNC/ERROR pin as a sync input");
+}
+
 def_reg!(Id, id, 0x07, 2);
 impl id::Data {
     pub fn id(&self) -> u16 {
diff --git a/firmware/src/main.rs b/firmware/src/main.rs
index 6f73f7e..2572e32 100644
--- a/firmware/src/main.rs
+++ b/firmware/src/main.rs
@@ -148,6 +148,7 @@ fn main() -> ! {
                 writeln!(stdout, "Corrupt ADC id: {:04X}", id).unwrap(),
         };
     }
+    adc.set_sync_enable(false).unwrap();
     // SENS0_{P,N}
     adc.setup_channel(0, ad7172::Input::Ain0, ad7172::Input::Ain1).unwrap();
     // SENS1_{P,N}