forked from M-Labs/ionpak-thermostat
ad7172: implement crc checksumming
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baab9b2d3f
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3bf1010969
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@ -132,9 +132,8 @@ impl<SPI> From<SPI> for AdcError<SPI> {
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#[repr(u8)]
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pub enum ChecksumMode {
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Off = 0b00,
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/// Seems much less reliable than `Crc`
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Xor = 0b01,
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/// Not implemented
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#[allow(unused)]
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Crc = 0b10,
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}
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@ -152,7 +151,15 @@ impl Checksum {
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ChecksumMode::Off => {},
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ChecksumMode::Xor => self.state ^= input,
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ChecksumMode::Crc => {
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// TODO
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for i in 0..8 {
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let input_mask = 0x80 >> i;
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self.state = (self.state << 1) ^
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if ((self.state & 0x80) != 0) != ((input & input_mask) != 0) {
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0x07 /* x8 + x2 + x + 1 */
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} else {
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0
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};
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}
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}
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}
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}
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@ -247,17 +254,17 @@ impl<SPI: Transfer<u8>, NSS: OutputPin> Adc<SPI, NSS> {
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fn write_reg<R: Register>(&mut self, reg: &R, reg_data: &mut R::Data) -> Result<(), AdcError<SPI::Error>> {
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let address = reg.address();
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let checksum_out = match self.checksum_mode {
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ChecksumMode::Off => None,
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ChecksumMode::Xor => {
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let mut xor = address;
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for b in reg_data.as_mut() {
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xor ^= *b;
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}
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Some(xor)
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}
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ChecksumMode::Crc => panic!("Not implemented"),
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};
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let mut checksum = Checksum::new(match self.checksum_mode {
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ChecksumMode::Off => ChecksumMode::Off,
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// write checksums are always crc
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ChecksumMode::Xor => ChecksumMode::Crc,
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ChecksumMode::Crc => ChecksumMode::Crc,
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});
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checksum.feed(address);
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for &mut b in reg_data.as_mut() {
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checksum.feed(b);
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}
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let checksum_out = checksum.result();
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self.transfer(address, reg_data.as_mut(), checksum_out)?;
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Ok(())
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}
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@ -116,8 +116,8 @@ fn main() -> ! {
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writeln!(stdout, "Corrupt ADC id: {:04X}", id).unwrap(),
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};
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}
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writeln!(stdout, "AD7172: setting checksum mode to XOR").unwrap();
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adc.set_checksum_mode(ad7172::ChecksumMode::Xor).unwrap();
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writeln!(stdout, "AD7172: setting checksum mode").unwrap();
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adc.set_checksum_mode(ad7172::ChecksumMode::Crc).unwrap();
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loop {
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let r = adc.identify();
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match r {
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