forked from M-Labs/ionpak-thermostat
strip more ionpak code
This commit is contained in:
parent
68e2b4634f
commit
1329c1567c
@ -9,81 +9,10 @@ pub mod delay;
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const LED1: u8 = 0x10; // PK4
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const LED2: u8 = 0x40; // PK6
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const FD_ADC: u8 = 0x01; // PE0
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const FV_ADC: u8 = 0x02; // PE1
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const FBI_ADC: u8 = 0x04; // PE2
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const IC_ADC: u8 = 0x08; // PE3
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const FBV_ADC: u8 = 0x20; // PD5
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const AV_ADC: u8 = 0x40; // PD6
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const FV_ERRN: u8 = 0x01; // PL0
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const FBV_ERRN: u8 = 0x02; // PL1
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const FBI_ERRN: u8 = 0x04; // PL2
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const AV_ERRN: u8 = 0x08; // PL3
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const AI_ERRN: u8 = 0x10; // PL4
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const ERR_LATCHN: u8 = 0x20; // PL5
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const BTNN: u8 = 0x80; // PL7
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const ERR_RESN: u8 = 0x01; // PQ0
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pub const PWM_LOAD: u16 = (/*pwmclk*/120_000_000u32 / /*freq*/100_000) as u16;
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const UART_DIV: u32 = (((/*sysclk*/120_000_000 * 8) / /*baud*/115200) + 1) / 2;
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pub const AV_ADC_GAIN: f32 = 6.792703150912105;
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pub const FV_ADC_GAIN: f32 = 501.83449105726623;
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pub const FBI_ADC_GAIN: f32 = 1333.3333333333333;
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pub const FBI_ADC_OFFSET: f32 = 96.0;
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pub const FD_ADC_GAIN: f32 = 3111.1111111111104;
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pub const FD_ADC_OFFSET: f32 = 96.0;
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pub const FBV_ADC_GAIN: f32 = 49.13796058269066;
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pub const FBV_PWM_GAIN: f32 = 0.07641071428571428;
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pub const IC_ADC_GAIN_LOW: f32 = 1333333333333.3333;
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pub const IC_ADC_GAIN_MED: f32 = 13201320132.0132;
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pub const IC_ADC_GAIN_HIGH: f32 = 133320001.3332;
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pub const IC_ADC_OFFSET: f32 = 96.0;
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pub const FBI_R223: f32 = 200.0;
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pub const FBI_R224: f32 = 39.0;
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pub const FBI_R225: f32 = 22000.0;
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pub fn reset_error() {
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cortex_m::interrupt::free(|_cs| {
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let gpio_q = unsafe { &*tm4c129x::GPIO_PORTQ::ptr() };
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gpio_q.data.modify(|r, w| w.data().bits(r.data().bits() & !ERR_RESN));
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gpio_q.data.modify(|r, w| w.data().bits(r.data().bits() | ERR_RESN));
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});
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}
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pub fn error_latched() -> bool {
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cortex_m::interrupt::free(|_cs| {
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let gpio_l = unsafe { &*tm4c129x::GPIO_PORTL::ptr() };
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gpio_l.data.read().bits() as u8 & ERR_LATCHN == 0
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})
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}
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pub fn process_errors() {
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let gpio_dat = cortex_m::interrupt::free(|_cs| {
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let gpio_l = unsafe { &*tm4c129x::GPIO_PORTL::ptr() };
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gpio_l.data.read().bits() as u8
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});
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if gpio_dat & FV_ERRN == 0 {
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println!("Filament overvolt");
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}
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if gpio_dat & FBV_ERRN == 0 {
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println!("Filament bias overvolt");
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}
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if gpio_dat & FBI_ERRN == 0 {
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println!("Filament bias overcurrent");
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}
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if gpio_dat & AV_ERRN == 0 {
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println!("Anode overvolt");
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}
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if gpio_dat & AI_ERRN == 0 {
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println!("Anode overcurrent");
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}
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}
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pub fn init() {
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cortex_m::interrupt::free(|_cs| {
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let sysctl = unsafe { &*tm4c129x::SYSCTL::ptr() };
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@ -217,51 +146,6 @@ pub fn init() {
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});
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}
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pub fn start_adc() {
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cortex_m::interrupt::free(|_cs| {
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let sysctl = unsafe { &*tm4c129x::SYSCTL::ptr() };
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let gpio_d = unsafe { &*tm4c129x::GPIO_PORTD_AHB::ptr() };
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let gpio_e = unsafe { &*tm4c129x::GPIO_PORTE_AHB::ptr() };
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gpio_d.afsel.write(|w| w.afsel().bits(FBV_ADC|AV_ADC));
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gpio_d.amsel.write(|w| w.amsel().bits(FBV_ADC|AV_ADC));
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gpio_e.afsel.write(|w| w.afsel().bits(FD_ADC|FV_ADC|FBI_ADC|IC_ADC));
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gpio_e.amsel.write(|w| w.amsel().bits(FD_ADC|FV_ADC|FBI_ADC|IC_ADC));
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sysctl.rcgcadc.modify(|_, w| w.r0().bit(true));
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while !sysctl.pradc.read().r0().bit() {}
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let adc0 = unsafe { &*tm4c129x::ADC0::ptr() };
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// VCO 480 / 15 = 32MHz ADC clock
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adc0.cc.write(|w| w.cs().syspll().clkdiv().bits(15-1));
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adc0.im.write(|w| w.mask0().bit(true));
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adc0.emux.write(|w| w.em0().always());
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adc0.ssmux0.write(|w| {
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w.mux0().bits(0) // IC_ADC
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.mux1().bits(1) // FBI_ADC
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.mux2().bits(2) // FV_ADC
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.mux3().bits(3) // FD_ADC
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.mux4().bits(5) // AV_ADC
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.mux5().bits(6) // FBV_ADC
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});
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adc0.ssctl0.write(|w| w.ie5().bit(true).end5().bit(true));
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adc0.sstsh0.write(|w| {
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w.tsh0()._4()
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.tsh1()._4()
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.tsh2()._4()
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.tsh3()._4()
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.tsh4()._4()
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.tsh5()._4()
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});
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adc0.sac.write(|w| w.avg()._64x());
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adc0.ctl.write(|w| w.vref().bit(true));
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adc0.actss.write(|w| w.asen0().bit(true));
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let mut cp = unsafe { tm4c129x::CorePeripherals::steal() };
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cp.NVIC.enable(tm4c129x::Interrupt::ADC0SS0);
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});
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}
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pub fn get_mac_address() -> [u8; 6] {
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let (userreg0, userreg1) = cortex_m::interrupt::free(|_cs| {
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let flashctl = unsafe { &*tm4c129x::FLASH_CTRL::ptr() };
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@ -1,93 +0,0 @@
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use eeprom;
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use crc::crc32;
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use smoltcp::wire::{IpCidr, IpAddress};
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const MAGIC: u8 = 0x54;
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struct EepromReader {
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buffer: [u8; eeprom::BLOCK_LEN]
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}
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impl EepromReader {
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fn new() -> EepromReader {
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EepromReader {
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buffer: [0; eeprom::BLOCK_LEN]
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}
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}
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fn read_payload_block<'a>(&'a mut self, block: u16) -> bool {
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eeprom::read_block(&mut self.buffer, block);
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if self.buffer[0] != MAGIC {
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return false;
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}
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let len = self.buffer.len();
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let cksum = self.buffer[len-4] as u32 | (self.buffer[len-3] as u32) << 8 |
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(self.buffer[len-2] as u32) << 16 | (self.buffer[len-1] as u32) << 24;
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if crc32::checksum_ieee(&self.buffer[0..len-4]) != cksum {
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return false;
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}
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true
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}
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fn read_payload<'a>(&'a mut self) -> Result<&'a [u8], ()> {
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let mut ok = self.read_payload_block(0);
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if !ok {
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ok = self.read_payload_block(1);
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}
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if ok {
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Ok(&self.buffer[1..self.buffer.len()-4])
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} else {
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Err(())
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}
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}
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}
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fn write_eeprom_payload(payload: &[u8]) {
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let mut buffer: [u8; eeprom::BLOCK_LEN] = [0; eeprom::BLOCK_LEN];
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buffer[0] = MAGIC;
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buffer[1..payload.len()+1].copy_from_slice(payload);
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let len = buffer.len();
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let cksum = crc32::checksum_ieee(&buffer[0..len-4]);
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buffer[len-4] = cksum as u8;
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buffer[len-3] = (cksum >> 8) as u8;
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buffer[len-2] = (cksum >> 16) as u8;
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buffer[len-1] = (cksum >> 24) as u8;
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eeprom::write_block(&buffer, 0);
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eeprom::write_block(&buffer, 1);
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}
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pub struct Config {
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pub ip: IpCidr,
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}
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impl Config {
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pub fn new() -> Config {
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Config {
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ip: IpCidr::new(IpAddress::v4(192, 168, 69, 1), 24)
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}
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}
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pub fn load(&mut self) {
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let mut reader = EepromReader::new();
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let payload = reader.read_payload();
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if payload.is_ok() {
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let payload = payload.unwrap();
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self.ip = IpCidr::new(
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IpAddress::v4(payload[0], payload[1], payload[2], payload[3]),
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payload[4])
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}
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}
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pub fn save(&self) {
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match self.ip {
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IpCidr::Ipv4(ipv4) => {
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let mut payload: [u8; 5] = [0; 5];
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payload[0..4].copy_from_slice(&ipv4.address().0);
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payload[4] = ipv4.prefix_len();
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write_eeprom_payload(&payload);
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}
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_ => panic!("unsupported network address")
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};
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}
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}
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@ -1,63 +0,0 @@
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use cortex_m::{self, asm::delay};
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use tm4c129x;
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pub const BLOCK_COUNT: u16 = 96;
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pub const BLOCK_LEN: usize = 64;
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fn wait_done() {
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while cortex_m::interrupt::free(|_cs| {
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let eeprom = unsafe { &*tm4c129x::EEPROM::ptr() };
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eeprom.eedone.read().working().bit()
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}) {};
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}
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pub fn init() {
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cortex_m::interrupt::free(|_cs| {
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let sysctl = unsafe { &*tm4c129x::SYSCTL::ptr() };
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sysctl.rcgceeprom.modify(|_, w| w.r0().bit(true)); // Bring up EEPROM
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delay(16);
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sysctl.sreeprom.modify(|_, w| w.r0().bit(true)); // Activate EEPROM reset
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delay(16);
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sysctl.sreeprom.modify(|_, w| w.r0().bit(false)); // Dectivate EEPROM reset
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delay(16);
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while !sysctl.preeprom.read().r0().bit() {} // Wait for the EEPROM to come out of reset
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delay(16);
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});
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wait_done();
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}
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pub fn read_block(buffer: &mut [u8; BLOCK_LEN], block: u16) {
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assert!(block < BLOCK_COUNT);
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cortex_m::interrupt::free(|_cs| {
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let eeprom = unsafe { &*tm4c129x::EEPROM::ptr() };
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eeprom.eeblock.write(|w| unsafe { w.block().bits(block) });
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eeprom.eeoffset.write(|w| unsafe { w.offset().bits(0) });
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for i in 0..BLOCK_LEN/4 {
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let word = eeprom.eerdwrinc.read().bits();
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buffer[4*i] = word as u8;
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buffer[4*i+1] = (word >> 8) as u8;
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buffer[4*i+2] = (word >> 16) as u8;
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buffer[4*i+3] = (word >> 24) as u8;
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}
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});
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}
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pub fn write_block(buffer: &[u8; BLOCK_LEN], block: u16) {
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assert!(block < BLOCK_COUNT);
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cortex_m::interrupt::free(|_cs| {
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let eeprom = unsafe { &*tm4c129x::EEPROM::ptr() };
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eeprom.eeblock.write(|w| unsafe { w.block().bits(block) });
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eeprom.eeoffset.write(|w| unsafe { w.offset().bits(0) });
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});
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for i in 0..BLOCK_LEN/4 {
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let word = buffer[4*i] as u32 | (buffer[4*i+1] as u32) << 8 |
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(buffer[4*i+2] as u32) << 16 | (buffer[4*i+3] as u32) << 24;
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cortex_m::interrupt::free(|_cs| {
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let eeprom = unsafe { &*tm4c129x::EEPROM::ptr() };
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eeprom.eerdwrinc.write(|w| unsafe { w.bits(word) });
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});
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delay(16);
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wait_done();
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}
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}
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@ -6,20 +6,17 @@ extern crate libm;
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extern crate cortex_m;
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#[macro_use]
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extern crate cortex_m_rt;
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#[macro_use(interrupt)]
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extern crate tm4c129x;
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extern crate smoltcp;
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extern crate crc;
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extern crate embedded_hal;
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extern crate nb;
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use core::cell::{Cell, RefCell};
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use core::fmt::{self, Write};
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use embedded_hal::digital::{InputPin, OutputPin};
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use embedded_hal::blocking::delay::DelayUs;
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use cortex_m::interrupt::Mutex;
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use smoltcp::time::Instant;
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use smoltcp::wire::EthernetAddress;
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use smoltcp::wire::{IpCidr, IpAddress, EthernetAddress};
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use smoltcp::iface::{NeighborCache, EthernetInterfaceBuilder};
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use smoltcp::socket::{SocketSet, TcpSocket, TcpSocketBuffer};
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@ -47,8 +44,6 @@ pub fn panic_fmt(info: &core::panic::PanicInfo) -> ! {
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#[macro_use]
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mod board;
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use board::gpio::Gpio;
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mod eeprom;
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mod config;
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mod ethmac;
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mod ad7172;
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@ -89,14 +84,6 @@ macro_rules! create_socket {
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fn main() -> ! {
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board::init();
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let mut config = config::Config::new();
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eeprom::init();
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/*if button_pressed {
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config.save();
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} else {
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config.load();
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}*/
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println!(r#"
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_ _
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(_) | |
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@ -128,7 +115,7 @@ fn main() -> ! {
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println!("programmed MAC address is invalid, using default");
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hardware_addr = EthernetAddress([0x10, 0xE2, 0xD5, 0x00, 0x03, 0x00]);
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}
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let mut ip_addrs = [config.ip];
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let mut ip_addrs = [IpCidr::new(IpAddress::v4(192, 168, 69, 1), 24)];
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println!("MAC {} IP {}", hardware_addr, ip_addrs[0]);
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let mut neighbor_cache_storage = [None; 8];
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let neighbor_cache = NeighborCache::new(&mut neighbor_cache_storage[..]);
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@ -187,7 +174,7 @@ fn main() -> ! {
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}
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})
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});
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for (&tcp_handle, pending) in (handles.iter().zip(socket_pending.iter_mut())) {
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for (&tcp_handle, pending) in handles.iter().zip(socket_pending.iter_mut()) {
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let socket = &mut *sockets.get::<TcpSocket>(tcp_handle);
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if !socket.is_open() {
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socket.listen(23).unwrap()
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