hartytp
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ionpak-thermostat
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strip more ionpak code

This commit is contained in:
Sebastien Bourdeauducq 2019-08-21 17:31:51 +08:00
parent 68e2b4634f
commit 1329c1567c
4 changed files with 3 additions and 288 deletions
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116
firmware/src/board/mod.rs
View File

@ -9,81 +9,10 @@ pub mod delay;
const LED1: u8 = 0x10; // PK4
const LED2: u8 = 0x40; // PK6
const FD_ADC: u8 = 0x01; // PE0
const FV_ADC: u8 = 0x02; // PE1
const FBI_ADC: u8 = 0x04; // PE2
const IC_ADC: u8 = 0x08; // PE3
const FBV_ADC: u8 = 0x20; // PD5
const AV_ADC: u8 = 0x40; // PD6
const FV_ERRN: u8 = 0x01; // PL0
const FBV_ERRN: u8 = 0x02; // PL1
const FBI_ERRN: u8 = 0x04; // PL2
const AV_ERRN: u8 = 0x08; // PL3
const AI_ERRN: u8 = 0x10; // PL4
const ERR_LATCHN: u8 = 0x20; // PL5
const BTNN: u8 = 0x80; // PL7
const ERR_RESN: u8 = 0x01; // PQ0
pub const PWM_LOAD: u16 = (/*pwmclk*/120_000_000u32 / /*freq*/100_000) as u16;
const UART_DIV: u32 = (((/*sysclk*/120_000_000 * 8) / /*baud*/115200) + 1) / 2;
pub const AV_ADC_GAIN: f32 = 6.792703150912105;
pub const FV_ADC_GAIN: f32 = 501.83449105726623;
pub const FBI_ADC_GAIN: f32 = 1333.3333333333333;
pub const FBI_ADC_OFFSET: f32 = 96.0;
pub const FD_ADC_GAIN: f32 = 3111.1111111111104;
pub const FD_ADC_OFFSET: f32 = 96.0;
pub const FBV_ADC_GAIN: f32 = 49.13796058269066;
pub const FBV_PWM_GAIN: f32 = 0.07641071428571428;
pub const IC_ADC_GAIN_LOW: f32 = 1333333333333.3333;
pub const IC_ADC_GAIN_MED: f32 = 13201320132.0132;
pub const IC_ADC_GAIN_HIGH: f32 = 133320001.3332;
pub const IC_ADC_OFFSET: f32 = 96.0;
pub const FBI_R223: f32 = 200.0;
pub const FBI_R224: f32 = 39.0;
pub const FBI_R225: f32 = 22000.0;
pub fn reset_error() {
cortex_m::interrupt::free(|_cs| {
let gpio_q = unsafe { &*tm4c129x::GPIO_PORTQ::ptr() };
gpio_q.data.modify(|r, w| w.data().bits(r.data().bits() & !ERR_RESN));
gpio_q.data.modify(|r, w| w.data().bits(r.data().bits() | ERR_RESN));
});
}
pub fn error_latched() -> bool {
cortex_m::interrupt::free(|_cs| {
let gpio_l = unsafe { &*tm4c129x::GPIO_PORTL::ptr() };
gpio_l.data.read().bits() as u8 & ERR_LATCHN == 0
})
}
pub fn process_errors() {
let gpio_dat = cortex_m::interrupt::free(|_cs| {
let gpio_l = unsafe { &*tm4c129x::GPIO_PORTL::ptr() };
gpio_l.data.read().bits() as u8
});
if gpio_dat & FV_ERRN == 0 {
println!("Filament overvolt");
}
if gpio_dat & FBV_ERRN == 0 {
println!("Filament bias overvolt");
}
if gpio_dat & FBI_ERRN == 0 {
println!("Filament bias overcurrent");
}
if gpio_dat & AV_ERRN == 0 {
println!("Anode overvolt");
}
if gpio_dat & AI_ERRN == 0 {
println!("Anode overcurrent");
}
}
pub fn init() {
cortex_m::interrupt::free(|_cs| {
let sysctl = unsafe { &*tm4c129x::SYSCTL::ptr() };
@ -217,51 +146,6 @@ pub fn init() {
});
}
pub fn start_adc() {
cortex_m::interrupt::free(|_cs| {
let sysctl = unsafe { &*tm4c129x::SYSCTL::ptr() };
let gpio_d = unsafe { &*tm4c129x::GPIO_PORTD_AHB::ptr() };
let gpio_e = unsafe { &*tm4c129x::GPIO_PORTE_AHB::ptr() };
gpio_d.afsel.write(|w| w.afsel().bits(FBV_ADC|AV_ADC));
gpio_d.amsel.write(|w| w.amsel().bits(FBV_ADC|AV_ADC));
gpio_e.afsel.write(|w| w.afsel().bits(FD_ADC|FV_ADC|FBI_ADC|IC_ADC));
gpio_e.amsel.write(|w| w.amsel().bits(FD_ADC|FV_ADC|FBI_ADC|IC_ADC));
sysctl.rcgcadc.modify(|_, w| w.r0().bit(true));
while !sysctl.pradc.read().r0().bit() {}
let adc0 = unsafe { &*tm4c129x::ADC0::ptr() };
// VCO 480 / 15 = 32MHz ADC clock
adc0.cc.write(|w| w.cs().syspll().clkdiv().bits(15-1));
adc0.im.write(|w| w.mask0().bit(true));
adc0.emux.write(|w| w.em0().always());
adc0.ssmux0.write(|w| {
w.mux0().bits(0) // IC_ADC
.mux1().bits(1) // FBI_ADC
.mux2().bits(2) // FV_ADC
.mux3().bits(3) // FD_ADC
.mux4().bits(5) // AV_ADC
.mux5().bits(6) // FBV_ADC
});
adc0.ssctl0.write(|w| w.ie5().bit(true).end5().bit(true));
adc0.sstsh0.write(|w| {
w.tsh0()._4()
.tsh1()._4()
.tsh2()._4()
.tsh3()._4()
.tsh4()._4()
.tsh5()._4()
});
adc0.sac.write(|w| w.avg()._64x());
adc0.ctl.write(|w| w.vref().bit(true));
adc0.actss.write(|w| w.asen0().bit(true));
let mut cp = unsafe { tm4c129x::CorePeripherals::steal() };
cp.NVIC.enable(tm4c129x::Interrupt::ADC0SS0);
});
}
pub fn get_mac_address() -> [u8; 6] {
let (userreg0, userreg1) = cortex_m::interrupt::free(|_cs| {
let flashctl = unsafe { &*tm4c129x::FLASH_CTRL::ptr() };

93
firmware/src/config.rs
View File

@ -1,93 +0,0 @@
use eeprom;
use crc::crc32;
use smoltcp::wire::{IpCidr, IpAddress};
const MAGIC: u8 = 0x54;
struct EepromReader {
buffer: [u8; eeprom::BLOCK_LEN]
}
impl EepromReader {
fn new() -> EepromReader {
EepromReader {
buffer: [0; eeprom::BLOCK_LEN]
}
}
fn read_payload_block<'a>(&'a mut self, block: u16) -> bool {
eeprom::read_block(&mut self.buffer, block);
if self.buffer[0] != MAGIC {
return false;
}
let len = self.buffer.len();
let cksum = self.buffer[len-4] as u32 | (self.buffer[len-3] as u32) << 8 |
(self.buffer[len-2] as u32) << 16 | (self.buffer[len-1] as u32) << 24;
if crc32::checksum_ieee(&self.buffer[0..len-4]) != cksum {
return false;
}
true
}
fn read_payload<'a>(&'a mut self) -> Result<&'a [u8], ()> {
let mut ok = self.read_payload_block(0);
if !ok {
ok = self.read_payload_block(1);
}
if ok {
Ok(&self.buffer[1..self.buffer.len()-4])
} else {
Err(())
}
}
}
fn write_eeprom_payload(payload: &[u8]) {
let mut buffer: [u8; eeprom::BLOCK_LEN] = [0; eeprom::BLOCK_LEN];
buffer[0] = MAGIC;
buffer[1..payload.len()+1].copy_from_slice(payload);
let len = buffer.len();
let cksum = crc32::checksum_ieee(&buffer[0..len-4]);
buffer[len-4] = cksum as u8;
buffer[len-3] = (cksum >> 8) as u8;
buffer[len-2] = (cksum >> 16) as u8;
buffer[len-1] = (cksum >> 24) as u8;
eeprom::write_block(&buffer, 0);
eeprom::write_block(&buffer, 1);
}
pub struct Config {
pub ip: IpCidr,
}
impl Config {
pub fn new() -> Config {
Config {
ip: IpCidr::new(IpAddress::v4(192, 168, 69, 1), 24)
}
}
pub fn load(&mut self) {
let mut reader = EepromReader::new();
let payload = reader.read_payload();
if payload.is_ok() {
let payload = payload.unwrap();
self.ip = IpCidr::new(
IpAddress::v4(payload[0], payload[1], payload[2], payload[3]),
payload[4])
}
}
pub fn save(&self) {
match self.ip {
IpCidr::Ipv4(ipv4) => {
let mut payload: [u8; 5] = [0; 5];
payload[0..4].copy_from_slice(&ipv4.address().0);
payload[4] = ipv4.prefix_len();
write_eeprom_payload(&payload);
}
_ => panic!("unsupported network address")
};
}
}

63
firmware/src/eeprom.rs
View File

@ -1,63 +0,0 @@
use cortex_m::{self, asm::delay};
use tm4c129x;
pub const BLOCK_COUNT: u16 = 96;
pub const BLOCK_LEN: usize = 64;
fn wait_done() {
while cortex_m::interrupt::free(|_cs| {
let eeprom = unsafe { &*tm4c129x::EEPROM::ptr() };
eeprom.eedone.read().working().bit()
}) {};
}
pub fn init() {
cortex_m::interrupt::free(|_cs| {
let sysctl = unsafe { &*tm4c129x::SYSCTL::ptr() };
sysctl.rcgceeprom.modify(|_, w| w.r0().bit(true)); // Bring up EEPROM
delay(16);
sysctl.sreeprom.modify(|_, w| w.r0().bit(true)); // Activate EEPROM reset
delay(16);
sysctl.sreeprom.modify(|_, w| w.r0().bit(false)); // Dectivate EEPROM reset
delay(16);
while !sysctl.preeprom.read().r0().bit() {} // Wait for the EEPROM to come out of reset
delay(16);
});
wait_done();
}
pub fn read_block(buffer: &mut [u8; BLOCK_LEN], block: u16) {
assert!(block < BLOCK_COUNT);
cortex_m::interrupt::free(|_cs| {
let eeprom = unsafe { &*tm4c129x::EEPROM::ptr() };
eeprom.eeblock.write(|w| unsafe { w.block().bits(block) });
eeprom.eeoffset.write(|w| unsafe { w.offset().bits(0) });
for i in 0..BLOCK_LEN/4 {
let word = eeprom.eerdwrinc.read().bits();
buffer[4*i] = word as u8;
buffer[4*i+1] = (word >> 8) as u8;
buffer[4*i+2] = (word >> 16) as u8;
buffer[4*i+3] = (word >> 24) as u8;
}
});
}
pub fn write_block(buffer: &[u8; BLOCK_LEN], block: u16) {
assert!(block < BLOCK_COUNT);
cortex_m::interrupt::free(|_cs| {
let eeprom = unsafe { &*tm4c129x::EEPROM::ptr() };
eeprom.eeblock.write(|w| unsafe { w.block().bits(block) });
eeprom.eeoffset.write(|w| unsafe { w.offset().bits(0) });
});
for i in 0..BLOCK_LEN/4 {
let word = buffer[4*i] as u32 | (buffer[4*i+1] as u32) << 8 |
(buffer[4*i+2] as u32) << 16 | (buffer[4*i+3] as u32) << 24;
cortex_m::interrupt::free(|_cs| {
let eeprom = unsafe { &*tm4c129x::EEPROM::ptr() };
eeprom.eerdwrinc.write(|w| unsafe { w.bits(word) });
});
delay(16);
wait_done();
}
}

19
firmware/src/main.rs
View File

@ -6,20 +6,17 @@ extern crate libm;
extern crate cortex_m;
#[macro_use]
extern crate cortex_m_rt;
#[macro_use(interrupt)]
extern crate tm4c129x;
extern crate smoltcp;
extern crate crc;
extern crate embedded_hal;
extern crate nb;
use core::cell::{Cell, RefCell};
use core::fmt::{self, Write};
use embedded_hal::digital::{InputPin, OutputPin};
use embedded_hal::blocking::delay::DelayUs;
use cortex_m::interrupt::Mutex;
use smoltcp::time::Instant;
use smoltcp::wire::EthernetAddress;
use smoltcp::wire::{IpCidr, IpAddress, EthernetAddress};
use smoltcp::iface::{NeighborCache, EthernetInterfaceBuilder};
use smoltcp::socket::{SocketSet, TcpSocket, TcpSocketBuffer};
@ -47,8 +44,6 @@ pub fn panic_fmt(info: &core::panic::PanicInfo) -> ! {
#[macro_use]
mod board;
use board::gpio::Gpio;
mod eeprom;
mod config;
mod ethmac;
mod ad7172;
@ -89,14 +84,6 @@ macro_rules! create_socket {
fn main() -> ! {
board::init();
let mut config = config::Config::new();
eeprom::init();
/*if button_pressed {
config.save();
} else {
config.load();
}*/
println!(r#"
_ _
(_) | |
@ -128,7 +115,7 @@ fn main() -> ! {
println!("programmed MAC address is invalid, using default");
hardware_addr = EthernetAddress([0x10, 0xE2, 0xD5, 0x00, 0x03, 0x00]);
}
let mut ip_addrs = [config.ip];
let mut ip_addrs = [IpCidr::new(IpAddress::v4(192, 168, 69, 1), 24)];
println!("MAC {} IP {}", hardware_addr, ip_addrs[0]);
let mut neighbor_cache_storage = [None; 8];
let neighbor_cache = NeighborCache::new(&mut neighbor_cache_storage[..]);
@ -187,7 +174,7 @@ fn main() -> ! {
}
})
});
for (&tcp_handle, pending) in (handles.iter().zip(socket_pending.iter_mut())) {
for (&tcp_handle, pending) in handles.iter().zip(socket_pending.iter_mut()) {
let socket = &mut *sockets.get::<TcpSocket>(tcp_handle);
if !socket.is_open() {
socket.listen(23).unwrap()