Discussion: Test Protocol Design v.1
Discussion: Test Protocol Design v.2
e79318171b
update misoc
c9efc20aeb
switch everything to nixpkgs 21.05
f595103f17
conda: fix access to bscan-spi-bitstreams
2355ba148a
openocd: use upstream nixpkgs version if recent enough
988d411946
mcu: simplify buildStm32Firmware
Test Report: Dual Sayma, DAC-to-DAC phase skew
DDMTD stability and HMC7043 phase slip failures need to be fully resolved before testing this.
In all previous test runs based off ARTIQ-7 (e.g. [single board DAC-DAC test on…
Test Report: Dual Sayma, DAC-to-DAC phase skew
2021-11-25
Conditions
- Hardware: unchanged, Sayma-2 AD9154-1 remain unused.
- ARTIQ: unchanged
- Testsuite: unchanged
Results
Sayma-1 AD9154-0 DAC1 -> Sayma-2 AD9154-1…
Test Report: Dual Sayma, DAC-to-DAC phase skew
2021-11-24
Conditions
- Hardware: Metlino as DRTIO master, 2 sets of Sayma (Sayma-1, Sayma-2) as DRTIO satellites (via uTCA carrier hub fabric)
- Sayma-2 AD9154-1 is not…
Test Report: Dual Sayma, DAC-to-DAC phase skew
RT: Supress in-line display of plaintext attachments
Test Report: Single Sayma, DAC-to-DAC phase skew
2021-10-06
Conditions
- Hardware: unchanged
- ARTIQ: unchanged
- Testsuite: 97cfcdf45d4d8bde5519cb11c6c720cd5cb4f5ca, except:
- In
test_mlabs
, all lines for RP power-cycling have…
- In