harry
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harry commented on issue harry/creotech-sayma-testsuite#2 2021-05-25 17:14:41 +08:00
Test Report: Single Sayma, DAC-to-DAC phase skew

2021-05-25

Conditions

  • Hardware: unchanged
  • ARTIQ: unchanged
  • Testsuite: unchanged

Results

  • # Test Runs: 15
  • # Test Run with Extreme Data:
    • Absolute phase skew…
harry commented on issue harry/creotech-sayma-testsuite#2 2021-05-25 16:57:59 +08:00
Test Report: Single Sayma, DAC-to-DAC phase skew

2021-05-24

Conditions

  • Hardware: added one extra Sayma as satellite 2, sharing the same gateware as the first Sayma; new Sayma NOT involved in this test
  • ARTIQ: unchanged *…
harry commented on issue harry/creotech-sayma-testsuite#2 2021-05-25 16:46:45 +08:00
Test Report: Single Sayma, DAC-to-DAC phase skew

2021-04-28

Conditions

  • Hardware: unchanged
  • ARTIQ: unchanged
  • Testsuite: unchanged

Results

  • # Test Runs: 13
  • # Test Run with Extreme Data:
    • BaseMod outputs no…
harry commented on issue harry/creotech-sayma-testsuite#2 2021-05-25 16:42:18 +08:00
Test Report: Single Sayma, DAC-to-DAC phase skew

2021-04-23

Conditions

  • Hardware: Metlino as DRTIO master, Sayma as DRTIO satellite (via uTCA carrier hub fabric)
  • ARTIQ: customized version…
harry opened issue harry/creotech-sayma-testsuite#2 2021-05-25 16:42:02 +08:00
Test Report: Single Sayma, DAC-to-DAC phase skew
harry pushed to master at M-Labs/nix-scripts 2021-05-21 11:45:55 +08:00
a6acfdca3a artiq-full: build ubirmingham3 drtio system
harry opened issue harry/creotech-sayma-testsuite#1 2021-05-13 11:36:41 +08:00
Discussion: Test Protocol Design
harry pushed to master at harry/creotech-sayma-testsuite 2021-05-13 10:37:35 +08:00
cb891b7719 Update README
cf8b40d629 Remove RP uhubctl power control scripts
ef463c32a5 Add script for OS shutdown on RP
62c74d5081 Update README
2bfa4326ab Remove RP uhubctl power control scripts
Compare 6 commits »
harry pushed to master at harry/creotech-sayma-testsuite 2021-05-13 10:35:49 +08:00
62c74d5081 Update README
509a8f0905 Update README
Compare 2 commits »
harry pushed to master at harry/creotech-sayma-testsuite 2021-05-13 10:34:49 +08:00
509a8f0905 Update README
2bfa4326ab Remove RP uhubctl power control scripts
140139edcb Add script for OS shutdown on RP
e46781a776 Add script for testing RP network connectivity
a5ba828b47 Add mlabs 2nd RP
Compare 5 commits »
harry pushed to master at harry/creotech-sayma-testsuite 2021-05-07 17:31:28 +08:00
001e981a65 rp_stop_uhubctl: Switch to SSH key auth for RP shutdown
harry pushed to master at harry/creotech-sayma-testsuite 2021-05-07 16:32:13 +08:00
698e90df1c Update README
0fc9309748 Add RP power control scripts
e5d24c9595 Update README
41066bcd16 Add RP power control scripts
Compare 4 commits »
harry pushed to master at harry/creotech-sayma-testsuite 2021-05-05 13:31:32 +08:00
e5d24c9595 Update README
41066bcd16 Add RP power control scripts
781cae28b4 Style
Compare 3 commits »
harry pushed to master at renet/ENC424J600 2021-04-30 17:30:45 +08:00
40a53cc0d6 spi: Fix Rx/Tx buffer logic & simplify
harry commented on issue renet/ENC424J600#9 2021-04-30 16:41:11 +08:00
Can SPI chip select timing be ensured without delay_ns?

Update:

  1. I read the datasheet more carefully and found two different types of valid CS behaviour:

    1. If there are contiguous transactions that are not fixed-length, CS must be…
harry pushed to master at renet/ENC424J600 2021-04-29 17:09:53 +08:00
6d17703e6b Add Enc424j600::init() for complete initialisation
78e4d82660 examples: Simplify & fix naming
b9b28f0725 Rename functions & classes for clarity
3529fcd192 Turn EthController trait methods unrelated to PHY into instance methods
Compare 4 commits »
harry pushed to master at harry/creotech-sayma-testsuite 2021-04-28 21:58:03 +08:00
c7f387f8d8 Update README
harry commented on issue renet/ENC424J600#9 2021-04-26 16:41:58 +08:00
Can SPI chip select timing be ensured without delay_ns?

To all reading this: most of my comments are for my own record and future reference. I am not requesting for any comments or answers from others, but if someone do I would greatly appreciate their…

harry commented on issue renet/ENC424J600#9 2021-04-26 16:33:18 +08:00
Can SPI chip select timing be ensured without delay_ns?

To clarify my thoughts and doubts:

  1. The issue on embedded_hal might still hold. On both Booster and my own testing firmware, CPU is…
harry commented on issue renet/ENC424J600#9 2021-04-26 16:32:15 +08:00
Can SPI chip select timing be ensured without delay_ns?

Hi Robert, it was stupid of me to phrase my question like this. Clearly, using a scope or logic analyser is suitable enough to check how CS changes w.r.t. data transactions (indicated by SCK…