forked from M-Labs/zynq-rs
270 lines
8.0 KiB
Rust
270 lines
8.0 KiB
Rust
#![no_std]
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#![no_main]
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#![feature(const_in_array_repeat_expressions)]
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extern crate alloc;
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use alloc::collections::BTreeMap;
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use libasync::{
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delay,
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smoltcp::{Sockets, TcpStream},
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task,
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};
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use libboard_zynq::{
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self as zynq,
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clocks::source::{ArmPll, ClockSource, IoPll},
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clocks::Clocks,
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print, println,
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mpcore,
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gic,
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smoltcp::{
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iface::{EthernetInterfaceBuilder, NeighborCache, Routes},
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time::Instant,
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wire::{EthernetAddress, IpAddress, IpCidr},
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},
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time::Milliseconds,
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};
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use libcortex_a9::{
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mutex::Mutex,
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sync_channel::{Sender, Receiver},
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sync_channel,
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};
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use libregister::RegisterR;
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use libsupport_zynq::{
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boot, ram,
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};
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use log::{info, warn};
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const HWADDR: [u8; 6] = [0, 0x23, 0xde, 0xea, 0xbe, 0xef];
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static mut CORE1_REQ: (Sender<usize>, Receiver<usize>) = sync_channel!(usize, 10);
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static mut CORE1_RES: (Sender<usize>, Receiver<usize>) = sync_channel!(usize, 10);
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#[no_mangle]
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pub fn main_core0() {
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// zynq::clocks::CpuClocks::enable_io(1_250_000_000);
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println!("\nzc706 main");
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// ps7_init::apply();
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libboard_zynq::stdio::drop_uart();
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libboard_zynq::logger::init().unwrap();
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log::set_max_level(log::LevelFilter::Trace);
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info!(
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"Boot mode: {:?}",
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zynq::slcr::RegisterBlock::new()
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.boot_mode
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.read()
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.boot_mode_pins()
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);
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#[cfg(feature = "target_zc706")]
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const CPU_FREQ: u32 = 800_000_000;
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#[cfg(feature = "target_cora_z7_10")]
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const CPU_FREQ: u32 = 650_000_000;
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info!("Setup clock sources...");
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ArmPll::setup(2 * CPU_FREQ);
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Clocks::set_cpu_freq(CPU_FREQ);
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#[cfg(feature = "target_zc706")]
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{
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IoPll::setup(1_000_000_000);
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libboard_zynq::stdio::drop_uart();
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}
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#[cfg(feature = "target_cora_z7_10")]
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{
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IoPll::setup(1_000_000_000);
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libboard_zynq::stdio::drop_uart();
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}
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info!("PLLs set up");
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let clocks = zynq::clocks::Clocks::get();
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info!(
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"CPU Clocks: {}/{}/{}/{}",
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clocks.cpu_6x4x(),
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clocks.cpu_3x2x(),
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clocks.cpu_2x(),
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clocks.cpu_1x()
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);
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let mut flash = zynq::flash::Flash::new(200_000_000).linear_addressing_mode();
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let flash_ram: &[u8] = unsafe { core::slice::from_raw_parts(flash.ptr(), flash.size()) };
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for i in 0..=1 {
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print!("Flash {}:", i);
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for b in &flash_ram[(i * 16 * 1024 * 1024)..][..128] {
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print!(" {:02X}", *b);
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}
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println!("");
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}
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let _flash = flash.stop();
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let timer = libboard_zynq::timer::GlobalTimer::start();
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let mut ddr = zynq::ddr::DdrRam::new();
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#[cfg(not(feature = "target_zc706"))]
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ddr.memtest();
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ram::init_alloc_ddr(&mut ddr);
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#[cfg(dev)]
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for i in 0..=1 {
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let mut flash_io = flash.manual_mode(i);
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// println!("rdcr={:02X}", flash_io.rdcr());
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print!("Flash {} ID:", i);
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for b in flash_io.rdid() {
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print!(" {:02X}", b);
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}
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println!("");
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print!("Flash {} I/O:", i);
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for o in 0..8 {
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const CHUNK: u32 = 8;
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for b in flash_io.read(CHUNK * o, CHUNK as usize) {
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print!(" {:02X}", b);
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}
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}
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println!("");
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flash_io.dump("Read cr1", 0x35);
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flash_io.dump("Read Autoboot", 0x14);
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flash_io.dump("Read Bank", 0x16);
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flash_io.dump("DLP Bank", 0x16);
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flash_io.dump("Read ESig", 0xAB);
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flash_io.dump("OTP Read", 0x4B);
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flash_io.dump("DYB Read", 0xE0);
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flash_io.dump("PPB Read", 0xE2);
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flash_io.dump("ASP Read", 0x2B);
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flash_io.dump("Password Read", 0xE7);
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flash_io.write_enabled(|flash_io| {
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flash_io.erase(0);
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});
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flash_io.write_enabled(|flash_io| {
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flash_io.program(0, [0x23054223; 0x100 >> 2].iter().cloned());
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});
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flash = flash_io.stop();
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}
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boot::Core1::start(false);
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let core1_req = unsafe { &mut CORE1_REQ.0 };
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let core1_res = unsafe { &mut CORE1_RES.1 };
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let mut interrupt_controller = gic::InterruptController::new(mpcore::RegisterBlock::new());
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interrupt_controller.enable_interrupts();
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task::block_on(async {
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for i in 0..10 {
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// this interrupt would cause core1 to reset.
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interrupt_controller.send_sgi(gic::InterruptId(0), gic::CPUCore::Core1.into());
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core1_req.async_send(i).await;
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let j = core1_res.async_recv().await;
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println!("{} -> {}", i, j);
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}
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});
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let eth = zynq::eth::Eth::default(HWADDR.clone());
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println!("Eth on");
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const RX_LEN: usize = 4096;
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// Number of transmission buffers (minimum is two because with
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// one, duplicate packet transmission occurs)
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const TX_LEN: usize = 4096;
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let eth = eth.start_rx(RX_LEN);
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let mut eth = eth.start_tx(TX_LEN);
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let ethernet_addr = EthernetAddress(HWADDR);
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// IP stack
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let local_addr = IpAddress::v4(192, 168, 1, 51);
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let mut ip_addrs = [IpCidr::new(local_addr, 24)];
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let routes = Routes::new(BTreeMap::new());
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let neighbor_cache = NeighborCache::new(BTreeMap::new());
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let mut iface = EthernetInterfaceBuilder::new(&mut eth)
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.ethernet_addr(ethernet_addr)
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.ip_addrs(&mut ip_addrs[..])
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.routes(routes)
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.neighbor_cache(neighbor_cache)
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.finalize();
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Sockets::init(32);
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const TCP_PORT: u16 = 19;
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// (rx, tx)
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let stats = alloc::rc::Rc::new(core::cell::RefCell::new((0, 0)));
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let stats_tx = stats.clone();
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task::spawn(async move {
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while let Ok(stream) = TcpStream::accept(TCP_PORT, 0x10_0000, 0x10_0000).await {
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let stats_tx = stats_tx.clone();
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task::spawn(async move {
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let tx_data = (0..=255).take(4096).collect::<alloc::vec::Vec<u8>>();
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loop {
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// const CHUNK_SIZE: usize = 65536;
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// match stream.send((0..=255).cycle().take(CHUNK_SIZE)).await {
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match stream.send_slice(&tx_data[..]).await {
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Ok(len) => stats_tx.borrow_mut().1 += tx_data.len(), //CHUNK_SIZE,
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Err(e) => {
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warn!("tx: {:?}", e);
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break
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}
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}
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}
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});
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}
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});
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let stats_rx = stats.clone();
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task::spawn(async move {
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while let Ok(stream) = TcpStream::accept(TCP_PORT+1, 0x10_0000, 0x10_0000).await {
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let stats_rx = stats_rx.clone();
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task::spawn(async move {
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loop {
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match stream.recv(|buf| (buf.len(), buf.len())).await {
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Ok(len) => stats_rx.borrow_mut().0 += len,
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Err(e) => {
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warn!("rx: {:?}", e);
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break
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}
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}
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}
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});
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}
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});
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let mut countdown = timer.countdown();
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task::spawn(async move {
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loop {
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delay(&mut countdown, Milliseconds(1000)).await;
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let timestamp = timer.get_us().0;
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let seconds = timestamp / 1_000_000;
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let micros = timestamp % 1_000_000;
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let (rx, tx) = {
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let mut stats = stats.borrow_mut();
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let result = *stats;
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*stats = (0, 0);
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result
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};
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info!("time: {:6}.{:06}s, rx: {}k/s, tx: {}k/s", seconds, micros, rx / 1024, tx / 1024);
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}
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});
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Sockets::run(&mut iface, || {
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Instant::from_millis(timer.get_time().0 as i64)
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})
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}
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static DONE: Mutex<bool> = Mutex::new(false);
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#[no_mangle]
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pub fn main_core1() {
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println!("Hello from core1!");
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let mut interrupt_controller = gic::InterruptController::new(mpcore::RegisterBlock::new());
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interrupt_controller.enable_interrupts();
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let req = unsafe { &mut CORE1_REQ.1 };
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let res = unsafe { &mut CORE1_RES.0 };
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for i in req {
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res.send(i * i);
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}
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println!("core1 done!");
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*DONE.lock() = true;
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loop {}
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}
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