eth: expose certain PHY reg for testing MDIO on experiments

experiments/src/main.rs

@@ -237,9 +237,38 @@ pub fn main_core0() {
         println!("");
     }
 
-    let eth = zynq::eth::Eth::default(HWADDR.clone());
+    let mut eth = zynq::eth::Eth::default(HWADDR.clone());
     println!("Eth on");
 
+    // Test Eth PHY Register Access
+    let phy_status = eth.get_status();
+    println!("Eth PHY register 1 bits 15-9: {}{}{}{}{}{}{}",
+        phy_status.cap_10base_t2_half() as u8, phy_status.cap_10base_t2_full() as u8,
+        phy_status.cap_10base_t_half() as u8, phy_status.cap_10base_t_full() as u8,
+        phy_status.cap_100base_tx_half() as u8, phy_status.cap_100base_tx_full() as u8,
+        phy_status.cap_100base_t4() as u8
+    );
+
+    info!("Testing Eth auto-negotiation: OFF");
+    eth.set_autoneg_enable(false);
+    let phy_control = eth.get_control();
+    println!("Eth PHY register 0 bit 12 (Auto-Negotiation Enable): {}",
+        phy_control.autoneg_enable() as u8
+    );
+    info!("Testing Eth speed: 100Mbps");
+    eth.set_speed1(false);
+    eth.set_speed0(true);
+    let phy_control = eth.get_control();
+    println!("Eth PHY register 0 bit 6, 13 (Speed): {} {}",
+        phy_control.speed1() as u8, phy_control.speed0() as u8
+    );
+    info!("Testing Eth duplex: OFF");
+    eth.set_duplex(false);
+    let phy_control = eth.get_control();
+    println!("Eth PHY register 0 bit 8 (Duplex): {}",
+        phy_control.duplex() as u8
+    );
+
     const RX_LEN: usize = 4096;
     // Number of transmission buffers (minimum is two because with
     // one, duplicate packet transmission occurs)

libboard_zynq/src/eth/mod.rs

@@ -353,6 +353,44 @@ impl<GEM: Gem, RX, TX> Eth<GEM, RX, TX> {
         );
         new_self
     }
+
+    /// Get access to PHY register 0 - Control
+    pub fn get_control(&mut self) -> phy::Control {
+        self.phy.get_control(&mut self.inner)
+    }
+
+    /// Get access to PHY register 1 - Status
+    pub fn get_status(&mut self) -> phy::Status {
+        self.phy.get_status(&mut self.inner)
+    }
+
+    /// Set PHY auto-negotiation enabled
+    pub fn set_autoneg_enable(&mut self, en: bool) -> () {
+        self.phy.modify_control(&mut self.inner, |control|
+            control.set_autoneg_enable(en)
+        )
+    }
+
+    /// Set PHY speed MSB (bit 6)
+    pub fn set_speed1(&mut self, boolean: bool) -> () {
+        self.phy.modify_control(&mut self.inner, |control|
+            control.set_speed1(boolean)
+        )
+    }
+
+    /// Set PHY speed LSB (bit 13)
+    pub fn set_speed0(&mut self, boolean: bool) -> () {
+        self.phy.modify_control(&mut self.inner, |control|
+            control.set_speed0(boolean)
+        )
+    }
+
+    /// Set PHY duplex
+    pub fn set_duplex(&mut self, en: bool) -> () {
+        self.phy.modify_control(&mut self.inner, |control|
+            control.set_duplex(en)
+        )
+    }
 }
 
 impl<GEM: Gem, TX> Eth<GEM, rx::DescList, TX> {