From e047c2900b0da0244aa05c22afd410106ef5636f Mon Sep 17 00:00:00 2001
From: Sebastien Bourdeauducq <sb@m-labs.hk>
Date: Fri, 1 May 2020 12:27:43 +0800
Subject: [PATCH] ddr: log clock info with debug level

---
 libboard_zynq/src/ddr/mod.rs | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/libboard_zynq/src/ddr/mod.rs b/libboard_zynq/src/ddr/mod.rs
index 37a9a26..23084c4 100644
--- a/libboard_zynq/src/ddr/mod.rs
+++ b/libboard_zynq/src/ddr/mod.rs
@@ -1,5 +1,5 @@
 use libregister::{RegisterR, RegisterW, RegisterRW};
-use log::{error, info};
+use log::{debug, info, error};
 use crate::{print, println};
 use super::slcr::{self, DdriobVrefSel};
 use super::clocks::{Clocks, source::{DdrPll, ClockSource}};
@@ -41,7 +41,7 @@ impl DdrRam {
         let clocks = Clocks::get();
         let ddr3x_clk_divisor = 2;
         let ddr2x_clk_divisor = 3;
-        info!("DDR 3x/2x clocks: {}/{}", clocks.ddr / u32::from(ddr3x_clk_divisor), clocks.ddr / u32::from(ddr2x_clk_divisor));
+        debug!("DDR 3x/2x clocks: {}/{}", clocks.ddr / u32::from(ddr3x_clk_divisor), clocks.ddr / u32::from(ddr2x_clk_divisor));
 
         slcr::RegisterBlock::unlocked(|slcr| {
             slcr.ddr_clk_ctrl.write(
@@ -62,7 +62,7 @@ impl DdrRam {
             .max(1).min(63) as u8;
         let divisor1 = ((DCI_FREQ - 1 + clocks.ddr) / DCI_FREQ / u32::from(divisor0))
             .max(1).min(63) as u8;
-        info!("DDR DCI clock: {} Hz", clocks.ddr / u32::from(divisor0) / u32::from(divisor1));
+        debug!("DDR DCI clock: {} Hz", clocks.ddr / u32::from(divisor0) / u32::from(divisor1));
 
         slcr::RegisterBlock::unlocked(|slcr| {
             // Step 1.