From cd8abae83994eb567e49a097255dadf2486b0cdd Mon Sep 17 00:00:00 2001
From: Astro <astro@spaceboyz.net>
Date: Mon, 22 Jun 2020 02:43:22 +0200
Subject: [PATCH] eth: fix cache maintenance

---
 experiments/src/main.rs     |  2 +-
 libboard_zynq/src/eth/rx.rs | 13 +++----------
 libboard_zynq/src/eth/tx.rs |  9 ++++-----
 3 files changed, 8 insertions(+), 16 deletions(-)

diff --git a/experiments/src/main.rs b/experiments/src/main.rs
index 7e371bf..b74a5e7 100644
--- a/experiments/src/main.rs
+++ b/experiments/src/main.rs
@@ -252,7 +252,7 @@ if false {
         while let Ok(stream) = TcpStream::accept(TCP_PORT, 0x10_0000, 0x10_0000).await {
             let stats_tx = stats_tx.clone();
             task::spawn(async move {
-                let tx_data = (0..=255).take(4096).collect::<alloc::vec::Vec<u8>>();
+                let tx_data = (0..=255).take(65536).collect::<alloc::vec::Vec<u8>>();
                 loop {
                     // const CHUNK_SIZE: usize = 65536;
                     // match stream.send((0..=255).cycle().take(CHUNK_SIZE)).await {
diff --git a/libboard_zynq/src/eth/rx.rs b/libboard_zynq/src/eth/rx.rs
index aedbb14..a47b174 100644
--- a/libboard_zynq/src/eth/rx.rs
+++ b/libboard_zynq/src/eth/rx.rs
@@ -83,10 +83,6 @@ impl DescList {
             entry.word1.write(
                 DescWord1::zeroed()
             );
-            // Flush buffer from cache, to be filled by the peripheral
-            // before next read
-            l2cache().clean_invalidate_slice(&buffer[..]);
-            dcci_slice(&buffer[..]);
         }
 
         DescList {
@@ -108,8 +104,9 @@ impl DescList {
             let word1 = entry.word1.read();
             let len = word1.frame_length_lsbs().into();
             let buffer = &mut self.buffers[self.next][0..len];
-            // l2cache().invalidate_slice(&mut buffer[..]);
-            // dcci_slice(&buffer[..]);
+            // Invalidate caches for packet buffer
+            l2cache().invalidate_slice(&mut buffer[..]);
+            dcci_slice(&buffer[..]);
 
             self.next += 1;
             if self.next >= list_len {
@@ -138,10 +135,6 @@ pub struct PktRef<'a> {
 
 impl<'a> Drop for PktRef<'a> {
     fn drop(&mut self) {
-        // Flush buffer from cache, to be filled by the peripheral
-        // before next read
-        l2cache().invalidate_slice(self.buffer);
-        dcci_slice(self.buffer);
 
         self.entry.word0.modify(|_, w| w.used(false));
         dmb();
diff --git a/libboard_zynq/src/eth/tx.rs b/libboard_zynq/src/eth/tx.rs
index a25a4a3..90a689d 100644
--- a/libboard_zynq/src/eth/tx.rs
+++ b/libboard_zynq/src/eth/tx.rs
@@ -1,6 +1,6 @@
 use core::ops::{Deref, DerefMut};
 use alloc::{vec, vec::Vec};
-use libcortex_a9::{cache::dcc_slice, UncachedSlice};
+use libcortex_a9::{asm::dmb, cache::dcc_slice, UncachedSlice};
 use libregister::*;
 use log::{debug, warn};
 use crate::l2cache;
@@ -95,7 +95,7 @@ impl DescList {
         // debug!("send {}", length);
         let list_len = self.list.len();
         let entry = &mut self.list[self.next];
-        // dmb();
+        dmb();
         if entry.word1.read().used() {
             let buffer = &mut self.buffers[self.next][0..length];
             entry.word1.write(DescWord1::zeroed()
@@ -129,13 +129,12 @@ pub struct PktRef<'a> {
 
 impl<'a> Drop for PktRef<'a> {
     fn drop(&mut self) {
-        // Write back all dirty cachelines of this buffer
+        // Write back all dirty cachelines of packet buffer
         dcc_slice(self.buffer);
         l2cache().clean_slice(self.buffer);
 
         self.entry.word1.modify(|_, w| w.used(false));
-        // dcci(self.entry);
-        // l2cache().clean_invalidate(self.entry);
+        dmb();
         // dsb();
         if ! self.regs.tx_status.read().tx_go() {
             // Start TX if not already running