From b2c707d54360d979ddc0156f42f359d710f525d0 Mon Sep 17 00:00:00 2001
From: Astro <astro@spaceboyz.net>
Date: Fri, 3 Jul 2020 02:17:43 +0200
Subject: [PATCH] ddr: remove superfluous `_reg` from register names

---
 libboard_zynq/src/ddr/mod.rs  |  2 +-
 libboard_zynq/src/ddr/regs.rs | 74 +++++++++++++++++------------------
 2 files changed, 38 insertions(+), 38 deletions(-)

diff --git a/libboard_zynq/src/ddr/mod.rs b/libboard_zynq/src/ddr/mod.rs
index d4166c4..4060d76 100644
--- a/libboard_zynq/src/ddr/mod.rs
+++ b/libboard_zynq/src/ddr/mod.rs
@@ -210,7 +210,7 @@ impl DdrRam {
     }
 
     pub fn status(&self) -> regs::ControllerStatus {
-        self.regs.mode_sts_reg.read().operating_mode()
+        self.regs.mode_sts.read().operating_mode()
     }
 
     pub fn ptr<T>(&mut self) -> *mut T {
diff --git a/libboard_zynq/src/ddr/regs.rs b/libboard_zynq/src/ddr/regs.rs
index c72842e..34e0e9e 100644
--- a/libboard_zynq/src/ddr/regs.rs
+++ b/libboard_zynq/src/ddr/regs.rs
@@ -29,59 +29,59 @@ pub enum ControllerStatus {
 pub struct RegisterBlock {
     pub ddrc_ctrl: DdrcCtrl,
     pub two_rank_cfg: RW<u32>,
-    pub hpr_reg: RW<u32>,
-    pub lpr_reg: RW<u32>,
-    pub wr_reg: RW<u32>,
-    pub dram_param_reg0: RW<u32>,
-    pub dram_param_reg1: RW<u32>,
-    pub dram_param_reg2: RW<u32>,
-    pub dram_param_reg3: RW<u32>,
-    pub dram_param_reg4: RW<u32>,
+    pub hpr: RW<u32>,
+    pub lpr: RW<u32>,
+    pub wr: RW<u32>,
+    pub dram_param0: RW<u32>,
+    pub dram_param1: RW<u32>,
+    pub dram_param2: RW<u32>,
+    pub dram_param3: RW<u32>,
+    pub dram_param4: RW<u32>,
     pub dram_init_param: RW<u32>,
-    pub dram_emr_reg: RW<u32>,
-    pub dram_emr_mr_reg: RW<u32>,
+    pub dram_emr: RW<u32>,
+    pub dram_emr_mr: RW<u32>,
     pub dram_burst8_rdwr: RW<u32>,
     pub dram_disable_dq: RW<u32>,
     pub dram_addr_map_bank: RW<u32>,
     pub dram_addr_map_col: RW<u32>,
     pub dram_addr_map_row: RW<u32>,
-    pub dram_odt_reg: RW<u32>,
-    pub phy_dbg_reg: RW<u32>,
+    pub dram_odt: RW<u32>,
+    pub phy_dbg: RW<u32>,
     pub phy_cmd_timeout_rddata_cpt: RW<u32>,
-    pub mode_sts_reg: ModeStsReg,
+    pub mode_sts: ModeStsReg,
     pub dll_calib: RW<u32>,
     pub odt_delay_hold: RW<u32>,
-    pub ctrl_reg1: RW<u32>,
-    pub ctrl_reg2: RW<u32>,
-    pub ctrl_reg3: RW<u32>,
-    pub ctrl_reg4: RW<u32>,
+    pub ctrl1: RW<u32>,
+    pub ctrl2: RW<u32>,
+    pub ctrl3: RW<u32>,
+    pub ctrl4: RW<u32>,
     _unused0: [RO<u32>; 2],
-    pub ctrl_reg5: RW<u32>,
-    pub ctrl_reg6: RW<u32>,
+    pub ctrl5: RW<u32>,
+    pub ctrl6: RW<u32>,
     _unused1: [RO<u32>; 8],
     pub che_refresh_timer01: RW<u32>,
     pub che_t_zq: RW<u32>,
-    pub che_t_zq_short_interval_reg: RW<u32>,
-    pub deep_pwrdwn_reg: RW<u32>,
+    pub che_t_zq_short_interval: RW<u32>,
+    pub deep_pwrdwn: RW<u32>,
     pub reg_2c: RW<u32>,
     pub reg_2d: RW<u32>,
     pub dfi_timing: RW<u32>,
     _unused2: [RO<u32>; 2],
-    pub che_ecc_control_reg_offset: RW<u32>,
-    pub che_corr_ecc_log_reg_offset: RW<u32>,
-    pub che_corr_ecc_addr_reg_offset: RW<u32>,
-    pub che_corr_ecc_data_31_0_reg_offset: RW<u32>,
-    pub che_corr_ecc_data_63_32_reg_offset: RW<u32>,
-    pub che_corr_ecc_data_71_64_reg_offset: RW<u32>,
-    pub che_uncorr_ecc_log_reg_offset: RW<u32>,
-    pub che_uncorr_ecc_addr_reg_offset: RW<u32>,
-    pub che_uncorr_ecc_data_31_0_reg_offset: RW<u32>,
-    pub che_uncorr_ecc_data_63_32_reg_offset: RW<u32>,
-    pub che_uncorr_ecc_data_71_64_reg_offset: RW<u32>,
-    pub che_ecc_stats_reg_offset: RW<u32>,
+    pub che_ecc_control_offset: RW<u32>,
+    pub che_corr_ecc_log_offset: RW<u32>,
+    pub che_corr_ecc_addr_offset: RW<u32>,
+    pub che_corr_ecc_data_31_0_offset: RW<u32>,
+    pub che_corr_ecc_data_63_32_offset: RW<u32>,
+    pub che_corr_ecc_data_71_64_offset: RW<u32>,
+    pub che_uncorr_ecc_log_offset: RW<u32>,
+    pub che_uncorr_ecc_addr_offset: RW<u32>,
+    pub che_uncorr_ecc_data_31_0_offset: RW<u32>,
+    pub che_uncorr_ecc_data_63_32_offset: RW<u32>,
+    pub che_uncorr_ecc_data_71_64_offset: RW<u32>,
+    pub che_ecc_stats_offset: RW<u32>,
     pub ecc_scrub: RW<u32>,
-    pub che_ecc_corr_bit_mask_31_0_reg_offset: RW<u32>,
-    pub che_ecc_corr_bit_mask_63_32_reg_offset: RW<u32>,
+    pub che_ecc_corr_bit_mask_31_0_offset: RW<u32>,
+    pub che_ecc_corr_bit_mask_63_32_offset: RW<u32>,
     _unused3: [RO<u32>; 5],
     pub phy_rcvr_enable: RW<u32>,
     pub phy_config0: RW<u32>,
@@ -134,7 +134,7 @@ pub struct RegisterBlock {
     _unused13: RO<u32>,
     pub dll_lock_sts: RW<u32>,
     pub phy_ctrl_sts: RW<u32>,
-    pub phy_ctrl_sts_reg2: RW<u32>,
+    pub phy_ctrl_sts2: RW<u32>,
     _unused14: [RO<u32>; 5],
     pub axi_id: RW<u32>,
     pub page_mask: RW<u32>,
@@ -151,7 +151,7 @@ pub struct RegisterBlock {
     pub excl_access_cfg1: RW<u32>,
     pub excl_access_cfg2: RW<u32>,
     pub excl_access_cfg3: RW<u32>,
-    pub mode_reg_read: RW<u32>,
+    pub mode_read: RW<u32>,
     pub lpddr_ctrl0: RW<u32>,
     pub lpddr_ctrl1: RW<u32>,
     pub lpddr_ctrl2: RW<u32>,