forked from M-Labs/zynq-rs
libboard_zynq: fix zc706 build
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@ -2,6 +2,8 @@ use libregister::{RegisterR, RegisterW, RegisterRW};
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use log::{debug, info, error};
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use crate::{print, println};
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use super::slcr;
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#[cfg(feature = "target_zc706")]
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use super::slcr::DdriobVrefSel;
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use super::clocks::{Clocks, source::{DdrPll, ClockSource}};
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mod regs;
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