Harry Ho fa0b190234 [WIP] Add preliminary ARTIQ scripts for ST1, ST2 ... * For ST2, add the argument `ttl_use_fpga=true` to disable generating 111ns pulses on the TTLs.		2021-03-09 17:02:10 +08:00
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device_db.py	Add ARTIQ device DB	2021-03-09 09:54:33 +08:00
manual_st1st2.py	[WIP] Add preliminary ARTIQ scripts for ST1, ST2	2021-03-09 17:02:10 +08:00