Discussion: Test Protocol Design v.1 #1

New Issue

harry · 2021-05-13T11:36:41+08:00

harry commented

2021-05-13 11:36:41 +08:00

I'd like to propose the following protocol for ST1 and ST2:

Test duration: 3m 30s
Test interval: 5m
Testing procedures:

Time (m:s) Task

0:00 Power on uTCA & RedPitaya(s)

2:00 Take measurement via RedPitaya(s) SCPI

3:00 Shut down RedPitaya OS

3:30 Power off uTCA & RedPitaya(s)

Here are some assumptions I made for this proposal:

The power supply for the uTCA and the RedPitaya(s) becomes available at the same instant as their power control scripts (e.g. power_strip/on.py//off.py on Creotech's setup) are executed from Shell.
When sending the SCPI commands, the delay for acquiring the signal waveforms from the RP is always constant.
Not more than 30s after issuing the OS shutdown command to the RP, the RP OS must go to the "soft-off" state. The state remains until the next test cycle.

Here are things that are not covered yet:

Methods to formally record and analyse all skew values measured, e.g. finding mean, STDEV, absolute deviation, plotting historgram.
Methods to detect and/or resolve possible RP issues, e.g. RP OS not running after power-on, SCPI server not responding to acquisition requests properly.
For ST2, what are the requirements for the TTL waveform? Should it be 9MHz (same as Sayma's AD9154), and should its phase accumulator begin at the same time as Metlino's RTIO core gets reset?

To implement ST3 and ST4, I believe we can follow similar testing procedures but take multiple measurements at regular intervals while both the uTCA and RP remains powered on. However, the temperature of RP might be a concern if it remains on for 24 hours.

I'd like to propose the following protocol for ST1 and ST2: * Test duration: 3m 30s * Test interval: 5m * Testing procedures: | Time (m:s) | Task | | ---------: | ---- | | 0:00 | Power on uTCA & RedPitaya(s) | | 2:00 | Take measurement via RedPitaya(s) SCPI | | 3:00 | Shut down RedPitaya OS | | 3:30 | Power off uTCA & RedPitaya(s) | Here are some assumptions I made for this proposal: 1. The power supply for the uTCA and the RedPitaya(s) becomes available at the same instant as their power control scripts (e.g. `power_strip/on.py`/`/off.py` on Creotech's setup) are executed from Shell. 2. When sending the SCPI commands, the delay for acquiring the signal waveforms from the RP is always constant. 3. Not more than 30s after issuing the OS shutdown command to the RP, the RP OS must go to the "soft-off" state. The state remains until the next test cycle. Here are things that are not covered yet: 1. Methods to formally record and analyse all skew values measured, e.g. finding mean, STDEV, absolute deviation, plotting historgram. 2. Methods to detect and/or resolve possible RP issues, e.g. RP OS not running after power-on, SCPI server not responding to acquisition requests properly. 3. For ST2, what are the requirements for the TTL waveform? Should it be 9MHz (same as Sayma's AD9154), and should its phase accumulator begin at the same time as Metlino's RTIO core gets reset? To implement ST3 and ST4, I believe we can follow similar testing procedures but take multiple measurements at regular intervals while both the uTCA and RP remains powered on. However, the temperature of RP might be a concern if it remains on for 24 hours.

harry added the

discussion

label 2021-05-13 11:36:41 +08:00

harry referenced this issue

2021-05-25 16:42:18 +08:00

Test Report: Single Sayma, DAC-to-DAC phase skew #2

harry referenced this issue

2021-05-25 16:57:59 +08:00

Test Report: Single Sayma, DAC-to-DAC phase skew #2

harry changed title from ~~Discussion: Test Protocol Design~~ to Discussion: Test Protocol Design v.1

2021-10-07 17:11:48 +08:00

harry referenced this issue