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Add ARTIQ device DB

This commit is contained in:
Harry Ho 2021-03-09 09:54:33 +08:00
parent 7909267b88
commit a0d92497a9
1 changed files with 109 additions and 0 deletions
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artiq_exp/device_db.py Normal file
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core_addr = "localhost"
device_db = {
"core": {
"type": "local",
"module": "artiq.coredevice.core",
"class": "Core",
"arguments": {"host": core_addr, "ref_period": 1/(8*150e6)}
},
"core_log": {
"type": "controller",
"host": "::1",
"port": 1068,
"command": "aqctl_corelog -p {port} --bind {bind} " + core_addr
},
"core_cache": {
"type": "local",
"module": "artiq.coredevice.cache",
"class": "CoreCache"
},
"core_dma": {
"type": "local",
"module": "artiq.coredevice.dma",
"class": "CoreDMA"
}
}
# master peripherals
# * None is needed.
"""
$ artiq_route metlino_routing.bin show
0: 0
1: 2 0
2: 2 1 0
3: 4 0
4: 4 1 0
"""
# DEST#1/2, #3/4 peripherals
for sayma in range(2):
amc_base = (sayma*0x020000) + 0x010000
rtm_base = (sayma*0x020000) + 0x020000
# MCX TTLs on Sayma AMC
for i in range(2):
device_db["ttl" + str(sayma*2+i)] = {
"type": "local",
"module": "artiq.coredevice.ttl",
"class": "TTLInOut",
"arguments": {"channel": amc_base + 4+i},
}
# Example on Sayma#1 RTM
# BaseMod0 RF switches starting at RTIO channel 0x000000
# BaseMod0 attenuator starting at RTIO channel 0x000004
# BaseMod1 RF switches starting at RTIO channel 0x000009
# BaseMod1 attenuator starting at RTIO channel 0x00000d
for basemod in range(2):
for i in range(4):
device_db["sawg_sw" + str(8*sayma + 4*basemod+i)] = {
"type": "local",
"module": "artiq.coredevice.ttl",
"class": "TTLOut",
"arguments": {"channel": rtm_base + basemod*9 + i}
}
att_idx = 2*sayma + basemod
device_db["basemod_att_rst_n"+str(att_idx)] = {
"type": "local",
"module": "artiq.coredevice.ttl",
"class": "TTLOut",
"arguments": {"channel": rtm_base + basemod*9 + 4}
}
device_db["basemod_att_clk"+str(att_idx)] = {
"type": "local",
"module": "artiq.coredevice.ttl",
"class": "TTLOut",
"arguments": {"channel": rtm_base + basemod*9 + 5}
}
device_db["basemod_att_le"+str(att_idx)] = {
"type": "local",
"module": "artiq.coredevice.ttl",
"class": "TTLOut",
"arguments": {"channel": rtm_base + basemod*9 + 6}
}
device_db["basemod_att_mosi"+str(att_idx)] = {
"type": "local",
"module": "artiq.coredevice.ttl",
"class": "TTLOut",
"arguments": {"channel": rtm_base + basemod*9 + 7}
}
device_db["basemod_att_miso"+str(att_idx)] = {
"type": "local",
"module": "artiq.coredevice.ttl",
"class": "TTLInOut",
"arguments": {"channel": rtm_base + basemod*9 + 8}
}
device_db["basemod_att"+str(att_idx)] = {
"type": "local",
"module": "artiq.coredevice.basemod_att",
"class": "BaseModAtt",
"arguments": {
"rst_n": "basemod_att_rst_n"+str(att_idx),
"clk": "basemod_att_clk"+str(att_idx),
"le": "basemod_att_le"+str(att_idx),
"mosi": "basemod_att_mosi"+str(att_idx),
"miso": "basemod_att_miso"+str(att_idx),
}
}