[WIP] Simplify ARTIQ scripts for DAC & TTL sync tests
* A single `SyncDDSTTL` experiment definition can be used to test DAC and TTL outputs. * For ST1/ST3, simply run this on Sayma gateware that produces hardcoded waves at SAWGs. * For ST2/ST4, either: * simply run this on Sayma gateware that produces hardcoded waves at both SAWGs and TTLs; or * set `gen_ttl_wave=true` and run this on Sayma gateware that produces hardcoded waves at SAWGs only, while both MCXs are used as TTLOuts.
This commit is contained in:
parent
db4ae51030
commit
64e85fc143
|
|
@ -47,7 +47,7 @@ for sayma in range(2):
|
||||||
device_db["ttl" + str(sayma*2+i)] = {
|
device_db["ttl" + str(sayma*2+i)] = {
|
||||||
"type": "local",
|
"type": "local",
|
||||||
"module": "artiq.coredevice.ttl",
|
"module": "artiq.coredevice.ttl",
|
||||||
"class": "TTLInOut",
|
"class": "TTLOut",
|
||||||
"arguments": {"channel": amc_base + 4+i},
|
"arguments": {"channel": amc_base + 4+i},
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -1,127 +0,0 @@
|
||||||
# NOTES:
|
|
||||||
# * Check DRTIO channel list by inspecting Metlino's log.
|
|
||||||
# * Prepare an artiq_route .CFG to route Sayma#1 and #2 as LINK#1,2 and #3,4.
|
|
||||||
|
|
||||||
from artiq.experiment import *
|
|
||||||
|
|
||||||
def build_st1st2(exp):
|
|
||||||
assert isinstance(exp, EnvExperiment)
|
|
||||||
|
|
||||||
exp.setattr_device("core")
|
|
||||||
# Test with SyncDDS channels
|
|
||||||
exp.basemods_1 = [exp.get_device("basemod_att"+str(i)) for i in range(2)]
|
|
||||||
exp.rfsws_1 = [exp.get_device("sawg_sw"+str(i)) for i in range(8)]
|
|
||||||
exp.basemods_2 = [exp.get_device("basemod_att"+str(i)) for i in range(2, 4)]
|
|
||||||
exp.rfsws_2 = [exp.get_device("sawg_sw"+str(i)) for i in range(8, 16)]
|
|
||||||
# Test with 2 TTL channels
|
|
||||||
exp.ttl_1 = exp.get_device("ttl0")
|
|
||||||
exp.ttl_2 = exp.get_device("ttl2")
|
|
||||||
# Bundled DUTs
|
|
||||||
exp.basemods = exp.basemods_1 + exp.basemods_2
|
|
||||||
exp.rfsws = exp.rfsws_1 + exp.rfsws_2
|
|
||||||
exp.ttls = [exp.ttl_1, exp.ttl_2]
|
|
||||||
|
|
||||||
|
|
||||||
class ST1(EnvExperiment):
|
|
||||||
def build(self):
|
|
||||||
build_st1st2(self)
|
|
||||||
|
|
||||||
@kernel
|
|
||||||
def drtio_is_up(self, drtio_index):
|
|
||||||
if not self.core.get_rtio_destination_status(drtio_index):
|
|
||||||
return False
|
|
||||||
print("DRTIO #", drtio_index, "is ready\n")
|
|
||||||
return True
|
|
||||||
|
|
||||||
@kernel
|
|
||||||
def run(self):
|
|
||||||
print("*** Waiting for DRTIO ready...")
|
|
||||||
drtio_indices = [1, 2, 3, 4]
|
|
||||||
for i in drtio_indices:
|
|
||||||
while not self.drtio_is_up(i):
|
|
||||||
pass
|
|
||||||
print("*** All DRTIO ready !")
|
|
||||||
|
|
||||||
self.core.reset()
|
|
||||||
|
|
||||||
for basemod in self.basemods:
|
|
||||||
basemod.reset()
|
|
||||||
delay(10*ms)
|
|
||||||
basemod.set(6.0, 6.0, 6.0, 6.0)
|
|
||||||
delay(10*ms)
|
|
||||||
# Printing shows that the BaseMod is being controlled properly.
|
|
||||||
print(basemod.get_mu())
|
|
||||||
delay(500*ms)
|
|
||||||
|
|
||||||
self.core.break_realtime()
|
|
||||||
for rfsw in self.rfsws:
|
|
||||||
rfsw.on()
|
|
||||||
delay(1*ms)
|
|
||||||
|
|
||||||
print("All RF switches are on.")
|
|
||||||
|
|
||||||
while True:
|
|
||||||
pass
|
|
||||||
|
|
||||||
|
|
||||||
class ST2(EnvExperiment):
|
|
||||||
def build(self):
|
|
||||||
build_st1st2(self)
|
|
||||||
# Option to switch TTL output source from RTIO PHY to FPGA (bypassing RTIO)
|
|
||||||
self.setattr_argument("ttl_use_fpga", BooleanValue(False))
|
|
||||||
|
|
||||||
@kernel
|
|
||||||
def drtio_is_up(self, drtio_index):
|
|
||||||
if not self.core.get_rtio_destination_status(drtio_index):
|
|
||||||
return False
|
|
||||||
print("DRTIO #", drtio_index, "is ready\n")
|
|
||||||
return True
|
|
||||||
|
|
||||||
@kernel
|
|
||||||
def run(self):
|
|
||||||
print("*** Waiting for DRTIO ready...")
|
|
||||||
drtio_indices = [1, 2, 3, 4]
|
|
||||||
for i in drtio_indices:
|
|
||||||
while not self.drtio_is_up(i):
|
|
||||||
pass
|
|
||||||
print("*** All DRTIO ready !")
|
|
||||||
|
|
||||||
self.core.reset()
|
|
||||||
|
|
||||||
for basemod in self.basemods:
|
|
||||||
basemod.reset()
|
|
||||||
delay(10*ms)
|
|
||||||
basemod.set(6.0, 6.0, 6.0, 6.0)
|
|
||||||
delay(10*ms)
|
|
||||||
# Printing shows that the BaseMod is being controlled properly.
|
|
||||||
print(basemod.get_mu())
|
|
||||||
delay(500*ms)
|
|
||||||
|
|
||||||
self.core.break_realtime()
|
|
||||||
for rfsw in self.rfsws:
|
|
||||||
rfsw.on()
|
|
||||||
delay(1*ms)
|
|
||||||
|
|
||||||
print("All RF switches are on.")
|
|
||||||
|
|
||||||
if self.ttl_use_fpga:
|
|
||||||
while True:
|
|
||||||
pass
|
|
||||||
else:
|
|
||||||
# test pulse
|
|
||||||
self.core.break_realtime()
|
|
||||||
for ttl in self.ttls:
|
|
||||||
ttl.output()
|
|
||||||
delay(1*ms)
|
|
||||||
|
|
||||||
print("TTLs are now outputting pulses.")
|
|
||||||
self.core.break_realtime()
|
|
||||||
while True:
|
|
||||||
with parallel:
|
|
||||||
for ttl in self.ttls:
|
|
||||||
ttl.on()
|
|
||||||
delay(111*ns)
|
|
||||||
with parallel:
|
|
||||||
for ttl in self.ttls:
|
|
||||||
ttl.off()
|
|
||||||
delay(4444*ns)
|
|
||||||
|
|
@ -0,0 +1,77 @@
|
||||||
|
# NOTES:
|
||||||
|
# * Check DRTIO channel list by inspecting Metlino's log.
|
||||||
|
# * Prepare an artiq_route .CFG to route Sayma#1 and #2 as LINK#1,2 and #3,4.
|
||||||
|
|
||||||
|
from artiq.experiment import *
|
||||||
|
|
||||||
|
def build_exp(exp):
|
||||||
|
assert isinstance(exp, EnvExperiment)
|
||||||
|
|
||||||
|
exp.setattr_device("core")
|
||||||
|
# Test with SyncDDS channels
|
||||||
|
exp.basemods_1 = [exp.get_device("basemod_att"+str(i)) for i in range(2)]
|
||||||
|
exp.rfsws_1 = [exp.get_device("sawg_sw"+str(i)) for i in range(8)]
|
||||||
|
exp.basemods_2 = [exp.get_device("basemod_att"+str(i)) for i in range(2, 4)]
|
||||||
|
exp.rfsws_2 = [exp.get_device("sawg_sw"+str(i)) for i in range(8, 16)]
|
||||||
|
# Test with 2 TTL channels
|
||||||
|
exp.ttl_1 = exp.get_device("ttl0")
|
||||||
|
exp.ttl_2 = exp.get_device("ttl2")
|
||||||
|
# Bundled DUTs
|
||||||
|
exp.basemods = exp.basemods_1 + exp.basemods_2
|
||||||
|
exp.rfsws = exp.rfsws_1 + exp.rfsws_2
|
||||||
|
exp.ttls = [exp.ttl_1, exp.ttl_2]
|
||||||
|
|
||||||
|
|
||||||
|
class SyncDDSTTL(EnvExperiment):
|
||||||
|
def build(self):
|
||||||
|
build_exp(self)
|
||||||
|
# Option to use RTIO to generate TTL output
|
||||||
|
self.setattr_argument("gen_ttl_wave", BooleanValue(False))
|
||||||
|
|
||||||
|
@kernel
|
||||||
|
def drtio_is_up(self, drtio_index):
|
||||||
|
if not self.core.get_rtio_destination_status(drtio_index):
|
||||||
|
return False
|
||||||
|
print("DRTIO #", drtio_index, "is ready\n")
|
||||||
|
return True
|
||||||
|
|
||||||
|
@kernel
|
||||||
|
def run(self):
|
||||||
|
print("*** Waiting for DRTIO ready...")
|
||||||
|
drtio_indices = [1, 2, 3, 4]
|
||||||
|
for i in drtio_indices:
|
||||||
|
while not self.drtio_is_up(i):
|
||||||
|
pass
|
||||||
|
print("*** All DRTIO ready !")
|
||||||
|
|
||||||
|
self.core.reset()
|
||||||
|
|
||||||
|
with parallel:
|
||||||
|
with sequential:
|
||||||
|
for basemod in self.basemods:
|
||||||
|
basemod.reset()
|
||||||
|
delay(10*ms)
|
||||||
|
basemod.set(6.0, 6.0, 6.0, 6.0)
|
||||||
|
delay(10*ms)
|
||||||
|
# Printing shows that the BaseMod is being controlled properly.
|
||||||
|
print(basemod.get_mu())
|
||||||
|
delay(500*ms)
|
||||||
|
delay(1*s)
|
||||||
|
for rfsw in self.rfsws:
|
||||||
|
rfsw.on()
|
||||||
|
delay(1*ms)
|
||||||
|
print("All RF switches are on, att = 6.0dB for each channel.")
|
||||||
|
|
||||||
|
if self.gen_ttl_wave:
|
||||||
|
# All MCX TTLs must be TTLOuts, not TTLInOuts
|
||||||
|
print("TTLs are now outputting pulses with RTIO.")
|
||||||
|
while True:
|
||||||
|
for ttl in self.ttls:
|
||||||
|
ttl.on()
|
||||||
|
delay(111*ns)
|
||||||
|
for ttl in self.ttls:
|
||||||
|
ttl.off()
|
||||||
|
delay(4444*ns)
|
||||||
|
|
||||||
|
while True:
|
||||||
|
pass
|
||||||
Loading…
Reference in New Issue