geekzjk
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  • Joined on 2021-06-10
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geekzjk pushed to master at sinara-hw/Syrostan 2021-06-30 14:51:35 +08:00
93ba0cbe9d HSADC: change from AC coupling to DC coupling; PCB: finish HSADC layout
17127387c9 PCB: optimize buck converter and shunt resistor layout
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geekzjk pushed to master at sinara-hw/Syrostan 2021-06-29 16:49:29 +08:00
26d727f8c5 PCB: replace LVDS resistors with 0201 package, optimize LVDS pairs layout
geekzjk pushed to master at sinara-hw/Syrostan 2021-06-29 10:38:15 +08:00
8ffd698079 PCB: optimize HSADC layout
geekzjk pushed to master at sinara-hw/Syrostan 2021-06-29 10:26:05 +08:00
6584f44f2a PCB: fix GND polygon dead zones; all: export BOM
geekzjk pushed to master at sinara-hw/Syrostan 2021-06-28 15:49:42 +08:00
10818a4771 PCB: fix small LVDS connection issue
geekzjk pushed to master at sinara-hw/Syrostan 2021-06-28 15:45:13 +08:00
a16bee581b PCB: fix small LVDS connection issue
geekzjk pushed to master at sinara-hw/Syrostan 2021-06-28 15:40:22 +08:00
185f9eacda PCB: finish routing
08bea50eb2 finish routing
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geekzjk pushed to master at sinara-hw/Syrostan 2021-06-28 15:34:22 +08:00
08bea50eb2 finish routing
53accc8761 PCB: finish IO and analog connectors
4b15f466a0 PCB: finish SWD, IIC
0e1120d266 FPGA: modify pin connections for convenient layout routing; PCB: finish FPGA IO, FSMC, ADC BUS, Power routing
2a31c8b3f3 PCB: finish LVDS routing
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geekzjk pushed to master at sinara-hw/Syrostan 2021-06-22 16:34:06 +08:00
6535ff5423 LVDS&IO: add fpga flash config; all: fix connection bugs; PCB: initialize component positions and layout
geekzjk pushed to master at sinara-hw/Syrostan 2021-06-22 09:45:17 +08:00
1df738664f all: update gitignore; remove redundant files
geekzjk pushed to master at sinara-hw/Syrostan 2021-06-21 17:06:41 +08:00
b740887ac2 HighSpeedADC: fix chip rotation bug, remove SMA connector; all: fix BJT base resistors; Power: remove DC jack; LVDS&IO: replace IDC header with dupont
982fefd6b5 all: update gitigore to fix symbol and footpin bugs; replace messy libs into one
327abdeb24 CurrentSensor: fix bugs and replace opamp with current senser
9bcc9a229b TestAutomation: replace messy wires with bus
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geekzjk pushed to master at sinara-hw/Syrostan 2021-06-18 16:27:43 +08:00
45940c1ac8 all: finish routing
9c10edde19 CurrentSensor: add mid point voltage reference; FPGA: fix pinout
0cebd6ed2b LVDS: add LVDS ports; all: add LEDs
74f4fc201a FPGA: add GPIO and ADC parallel port
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geekzjk pushed to master at sinara-hw/Syrostan 2021-06-17 17:33:16 +08:00
9a62476f9e MCU: finish connectors
geekzjk pushed to master at sinara-hw/Syrostan 2021-06-17 15:49:29 +08:00
4123caa996 all: add gitignore; remove redundant files from repo; optimize file name style
ea24a86bbe all: add gitignore; remove redundant files from repo; optimize file name style
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geekzjk pushed to master at sinara-hw/Syrostan 2021-06-17 15:48:07 +08:00
ea24a86bbe all: add gitignore; remove redundant files from repo; optimize file name style
33a31d6db2 all: remove redundant files from repo; optimize file name style
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geekzjk pushed to master at sinara-hw/Syrostan 2021-06-17 15:46:06 +08:00
33a31d6db2 all: remove redundant files from repo; optimize file name style
geekzjk pushed to master at sinara-hw/Syrostan 2021-06-17 15:35:57 +08:00
6cee2d0419 Current_Senser: add current sampling; all: optimize +3.3VA
9f7ffb7754 docs: remove unused Chinese docs
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geekzjk pushed to master at sinara-hw/Syrostan 2021-06-17 10:52:37 +08:00
dfe4255a21 MCU: finish FSMC, PWM
geekzjk created branch master in sinara-hw/Syrostan 2021-06-16 17:34:31 +08:00
geekzjk pushed to master at sinara-hw/Syrostan 2021-06-16 17:34:31 +08:00
fc8c667020 Power: fix hierarchical and global label
5b4801ff74 FPGA: finish EEM, I2C, CFG, SPI FLASH
fc2cb47610 all: map symbol and footpins
24471104a5 Analog_LVDS: finish ADC
66188cd3ad Ethernet: finish ethernet controller and PoE input
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