forked from M-Labs/zynq-rs
zynq::ddr: optimize memtest
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@ -1,5 +1,5 @@
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use crate::regs::{RegisterR, RegisterW, RegisterRW};
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use crate::println;
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use crate::{print, println};
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use super::slcr;
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use super::clocks::CpuClocks;
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@ -178,7 +178,7 @@ impl DdrRam {
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}
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// TODO: move into trait
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pub fn ptr(&mut self) -> *mut u8 {
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pub fn ptr<T>(&mut self) -> *mut T {
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0x0010_0000 as *mut _
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}
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@ -195,28 +195,27 @@ impl DdrRam {
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let slice = unsafe {
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core::slice::from_raw_parts_mut(self.ptr(), self.size())
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};
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let patterns: &'static [u8] = &[0, 0xff, 0x55, 0xaa, 0];
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let patterns: &'static [u32] = &[0xffff_ffff, 0x5555_5555, 0xaaaa_aaaa, 0];
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let mut expected = None;
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for (i, pattern) in patterns.iter().enumerate() {
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println!("memtest phase {} (status: {:?})", i, self.status());
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// shift by 7 bits to be able to multiply with 100 (%)
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let progress_max = (slice.len() >> 7) - 1;
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let mut progress = 0;
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for (j, b) in slice.iter_mut().enumerate() {
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expected.map(|expected| {
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let read: u8 = *b;
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if read != expected {
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println!("{:08X}: expected {:02X}, read {:02X}", b as *mut u8 as usize, expected, read);
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}
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});
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*b = *pattern;
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let new_progress = 100 * (j >> 7) / progress_max;
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if new_progress != progress {
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progress = new_progress;
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println!("{}%", progress);
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for megabyte in 0..=(slice.len() / (1024 * 1024)) {
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let start = megabyte * 1024 * 1024 / 4;
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let end = ((megabyte + 1) * 1024 * 1024 / 4).min(slice.len());
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for b in slice[start..end].iter_mut() {
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expected.map(|expected| {
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let read: u32 = *b;
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if read != expected {
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println!("{:08X}: expected {:08X}, read {:08X}", b as *mut _ as usize, expected, read);
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}
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});
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*b = *pattern;
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}
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print!("\r{} MB", megabyte);
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}
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println!(" Ok");
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expected = Some(*pattern);
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}
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