fsagbuya/zynq-rs
1
0
Fork 0
forked from M-Labs/zynq-rs
Code Pull Requests Activity

compile fixes

Browse Source
This commit is contained in:
Astro 2019-07-01 00:15:17 +02:00
parent 5a8d714627
commit b9c233b05b
2 changed files with 2 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
src/eth/mod.rs
View File

@ -1,5 +1,6 @@
use crate::regs::*;
use crate::slcr;
use crate::println;
pub mod phy;
mod regs;

2
src/eth/tx.rs
View File

@ -1,5 +1,6 @@
use core::ops::{Deref, DerefMut};
use crate::{register, register_bit, register_bits, register_bits_typed, regs::*};
use crate::println;
use super::{MTU, regs};
/// Descriptor entry
@ -52,7 +53,6 @@ impl<'a> DescList<'a> {
// every frame contains 1 packet
.last_buffer(true)
);
);
}
DescList {