forked from M-Labs/zynq-rs
boot: ACTLR.enable_smp()
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@ -52,6 +52,10 @@ unsafe fn boot_core0() -> ! {
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.setup_flat_layout();
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mmu::with_mmu(mmu_table, || {
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mpcore.scu_control.start();
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ACTLR.enable_smp();
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// TODO: Barriers reqd when core1 is not yet starting?
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asm::dmb();
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asm::dsb();
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crate::main();
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panic!("return from main");
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@ -68,6 +72,11 @@ unsafe fn boot_core1() -> ! {
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let mmu_table = mmu::L1Table::get();
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mmu::with_mmu(mmu_table, || {
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ACTLR.enable_smp();
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// TODO: Barriers reqd when core1 is not yet starting?
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asm::dmb();
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asm::dsb();
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crate::main_core1();
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panic!("return from main_core1");
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});
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@ -1,5 +1,5 @@
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use crate::{register_bit, register_bits};
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use crate::regs::{RegisterR, RegisterW};
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use crate::regs::{RegisterR, RegisterW, RegisterRW};
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macro_rules! def_reg_r {
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($name:tt, $type: ty, $asm_instr:tt) => {
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@ -115,6 +115,36 @@ register_bit!(sctlr,
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/// Thumb Exception Enable
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te, 30);
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/// Auxiliary Control Register
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pub struct ACTLR;
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wrap_reg!(actlr);
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def_reg_r!(ACTLR, actlr::Read, "mrc p15, 0, $0, c1, c0, 1");
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def_reg_w!(ACTLR, actlr::Write, "mcr p15, 0, $0, c1, c0, 1");
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// SMP bit
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register_bit!(actlr, parity_on, 9);
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register_bit!(actlr, alloc_one_way, 8);
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register_bit!(actlr, excl, 7);
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register_bit!(actlr, smp, 6);
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register_bit!(actlr, write_full_line_of_zeros, 3);
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register_bit!(actlr, l1_prefetch_enable, 2);
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// Cache/TLB maintenance broadcast
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register_bit!(actlr, fw, 0);
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impl RegisterRW for ACTLR {
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fn modify<F: FnOnce(Self::R, Self::W) -> Self::W>(&mut self, f: F) {
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let r = self.read();
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let w = actlr::Write { inner: r.inner };
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let w = f(r, w);
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self.write(w);
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}
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}
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impl ACTLR {
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pub fn enable_smp(&mut self) {
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self.modify(|_, w| w.smp(true).fw(true));
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}
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}
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/// Domain Access Control Register
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pub struct DACR;
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def_reg_r!(DACR, u32, "mrc p15, 0, $0, c3, c0, 0");
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