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zynq-rs
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sdcard: Changed some debug to trace.

This commit is contained in:
pca006132 2020-06-15 16:47:47 +08:00
parent e0f26871db
commit a17a5d2925
1 changed files with 3 additions and 3 deletions
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6
libboard_zynq/src/sdio/sd_card.rs
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@ -112,7 +112,7 @@ impl SdCard {
let mut csd: [u32; 4] = [0, 0, 0, 0]; let mut csd: [u32; 4] = [0, 0, 0, 0];
for i in 0..=3 { for i in 0..=3 {
csd[i] = self.sdio.regs.responses[i].read(); csd[i] = self.sdio.regs.responses[i].read();
debug!("CSD[{}] = {:0X}", i, csd[i]); trace!("CSD[{}] = {:0X}", i, csd[i]);
} }
const CSD_STRUCT_MSK: u32 = 0x00C00000; const CSD_STRUCT_MSK: u32 = 0x00C00000;
@ -350,13 +350,13 @@ impl SdCard {
} }
fn wait_transfer_complete(&mut self) -> Result<(), CmdTransferError> { fn wait_transfer_complete(&mut self) -> Result<(), CmdTransferError> {
debug!("Wait for transfer complete"); trace!("Wait for transfer complete");
let mut status = self.sdio.regs.interrupt_status.read(); let mut status = self.sdio.regs.interrupt_status.read();
while !status.transfer_complete() { while !status.transfer_complete() {
self.sdio.check_error(&status)?; self.sdio.check_error(&status)?;
status = self.sdio.regs.interrupt_status.read(); status = self.sdio.regs.interrupt_status.read();
} }
debug!("Clearing transfer complete"); trace!("Clearing transfer complete");
self.sdio self.sdio
.regs .regs
.interrupt_status .interrupt_status