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zynq-rs
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zynq::{ddr, eth}: fix clock divisor calculation 

off-by-one, didn't change behavior.
This commit is contained in:
Astro 2019-11-03 02:22:41 +01:00
parent 04e816d99e
commit 961e2e1dd0
2 changed files with 6 additions and 6 deletions
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4
src/zynq/ddr/mod.rs
View File

@ -56,9 +56,9 @@ impl DdrRam {
/// Zynq-7000 AP SoC Technical Reference Manual:
/// 10.6.2 DDR IOB Impedance Calibration
fn calibrate_iob_impedance(clocks: &CpuClocks) {
let divisor0 = (clocks.ddr / DCI_FREQ)
let divisor0 = ((DCI_FREQ - 1 + clocks.ddr) / DCI_FREQ)
.max(1).min(63) as u8;
let divisor1 = 1 + (clocks.ddr / DCI_FREQ / u32::from(divisor0))
let divisor1 = (clocks.ddr / DCI_FREQ / u32::from(divisor0))
.max(1).min(63) as u8;
let slcr = slcr::RegisterBlock::new();

8
src/zynq/eth/mod.rs
View File

@ -192,8 +192,8 @@ impl<'r> Eth<'r, (), ()> {
impl<'r, RX, TX> Eth<'r, RX, TX> {
pub fn setup_gem0_clock(tx_clock: u32) {
let io_pll = CpuClocks::get().io;
let d0 = (io_pll / tx_clock).min(63);
let d1 = (io_pll / tx_clock / d0).min(63);
let d0 = ((tx_clock - 1 + io_pll) / tx_clock).max(1).min(63);
let d1 = (io_pll / tx_clock / d0).max(1).min(63);
let slcr = slcr::RegisterBlock::new();
slcr.gem0_clk_ctrl.write(
@ -215,8 +215,8 @@ impl<'r, RX, TX> Eth<'r, RX, TX> {
pub fn setup_gem1_clock(tx_clock: u32) {
let io_pll = CpuClocks::get().io;
let d0 = (io_pll / tx_clock).min(63);
let d1 = (io_pll / tx_clock / d0).min(63);
let d0 = ((tx_clock - 1 + io_pll) / tx_clock).max(1).min(63);
let d1 = (io_pll / tx_clock / d0).max(1).min(63);
let slcr = slcr::RegisterBlock::new();
slcr.gem1_clk_ctrl.write(