forked from M-Labs/nix-servo
linuswck
90f18a2a00
- Si5340 should be initialized first before calling any PL register since if
Si5340 is not preprogrammed, there is not PL system clock driving any PL register.
- Adc Initialization causes the PL MMCM to relock and trigger a global PL reset. Thus,
CSR registers should only be altered after Adc is initialized successfully.
210 lines
7.2 KiB
Python
210 lines
7.2 KiB
Python
# This file is part of Fast Servo Software Package.
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#
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# Copyright (C) 2023 Jakub Matyas
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# Warsaw University of Technology <jakubk.m@gmail.com>
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# SPDX-License-Identifier: GPL-3.0-or-later
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#
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# This program is free software: you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation, either version 3 of the License, or
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# (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program. If not, see <https://www.gnu.org/licenses/>.
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import time
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import spidev
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from pyfastservo.common import (
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CH0_HIGH_WORD_ADDR,
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CH0_LOW_WORD_ADDR,
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CH1_HIGH_WORD_ADDR,
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CH1_LOW_WORD_ADDR,
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CTRL_ADDR,
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MAP_MASK,
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PAGESIZE,
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write_to_memory,
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read_from_memory
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)
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# /dev/spidev2.0 <=> spidev<BUS>.<DEVICE>
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MAIN_DAC_BUS = 2
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MAIN_DAC_DEVICE = 0
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DAC_VERSION = 0x0A
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def inc_ddr_clk_phase():
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curr_cfg = read_from_memory(CTRL_ADDR, 1)[0] & 0x07
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write_to_memory(CTRL_ADDR, 0x10 | curr_cfg) # Set MMCM Phase Shift to be INC
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write_to_memory(CTRL_ADDR, 0x18 | curr_cfg) # Assert MMCM Phase Shift EN High
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write_to_memory(CTRL_ADDR, curr_cfg) # Deassert MMCM Phase Shift EN High
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def dec_ddr_clk_phase():
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curr_cfg = read_from_memory(CTRL_ADDR, 1)[0] & 0x07
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write_to_memory(CTRL_ADDR, 0x00 | curr_cfg) # Set MMCM Phase Shift to be DEC
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write_to_memory(CTRL_ADDR, 0x08 | curr_cfg) # Assert MMCM Phase Shift EN High
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write_to_memory(CTRL_ADDR, curr_cfg) # Deassert MMCM Phase Shift EN High
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def spi_write(spi, address, value):
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spi.xfer2([address, value])
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def spi_read(spi, address):
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rx_buffer = spi.xfer2([0x80 | address, 0x00])
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return rx_buffer[1]
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def verify_registers_vals(spi, reg_to_check):
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for register, expected_value in reg_to_check.items():
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value = spi_read(spi, register)
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if value != expected_value:
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print(f"Different value read than sent in reg 0x{register:02x}. Expected: 0x{expected_value:02x} Got: 0x{value:02x}")
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return False
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return True
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def soft_reset(spi):
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spi_write(spi, 0x00, 0x10) # Software reset
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spi_write(spi, 0x00, 0x00) # Release software reset
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spi_read(spi, 0x00) # Read reset address (necessary for reset to take effect)
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def check_version(spi):
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version = spi_read(spi, 0x1F)
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print(f"DAC version: 0x{version:02X}")
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return version == DAC_VERSION
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def configure_dac(spi):
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register_settings = {
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0x01: 0x40, # Clear EXTREF bit for internal reference,
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0x02: 0xB4, # Enable 2's complement, IFirst: True, IRising: True, DCI_EN: Enabled
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0x0D: 0x00, # Set RREF to 10 kΩ for 1.0V reference
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0x04: 0xA0, # Enable on-chip IRSET (1.6 kΩ for 20mA output)
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0x07: 0xA0, # Enable on-chip QRSET (1.6 kΩ for 20mA output)
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0x05: 0x00, # Disable internal IRCML
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0x08: 0x00, # Disable internal QRCML
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}
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for addr, val in register_settings.items():
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spi_write(spi, addr, val)
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success = verify_registers_vals(spi, register_settings)
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if success:
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# Set manual override output default back to 0V in 2's complement
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set_dac_input_override_value(0x0000)
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return success
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def dac_self_calibration(spi):
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spi_write(spi, 0x12, 0x00) # Reset calibration status
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spi_write(spi, 0x0E, 0x08) # Enable calibration clock, default divide ratio
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spi_write(spi, 0x0E, 0x38) # CALSELI = 1, CALSELQ = 1, CALCLK = 1
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spi_write(spi, 0x12, 0x10) # Set CALEN bit
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while True:
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status = spi_read(spi, 0x0F)
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if status & 0xC0 == 0xC0: # Both CALSTATI and CALSTATQ are 1
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break
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time.sleep(0.01)
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spi_write(spi, 0x12, 0x00) # Clear calibration bits
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spi_write(spi, 0x0E, 0x30) # Keep CALSELI and CALSELQ set, clear CALCLK
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print("DAC self-calibration completes")
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return True
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def set_dac_input_override(enable=True):
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# It is enabled by default after PL reset.
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# Disable it during PL init to routes the DAC output from linien-server
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reg_contents = read_from_memory(CTRL_ADDR, 1)[0]
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to_write = reg_contents | 0b1 if enable else reg_contents & 0b110
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write_to_memory(CTRL_ADDR, to_write)
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print(f"Enable DAC Input Override: {enable}")
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def power_down_afe(channel, power_down=True):
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# It is enabled by default after PL reset.
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# Disable it during PL init
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assert channel in (0, 1)
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bitmask = 1 << (channel + 1) & 0b111
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reg_contents = read_from_memory(CTRL_ADDR, 1)[0]
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value = (1 if power_down else 0) << (channel + 1)
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reg_contents &= ~bitmask
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to_write = reg_contents | value
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write_to_memory(CTRL_ADDR, to_write)
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reg_contents = read_from_memory(CTRL_ADDR, 1)[0]
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print(f"Power Down DAC AFE Ch{channel}: {power_down}")
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def set_dac_input_override_value(value):
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value = min(value, 0x3FFF)
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low_word = value & 0xFF
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high_word = (value >> 8) & 0x3F
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# Note: DAC HIGH word and LOW word output are not updated
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# at the same time. On scope, you will see more than one step
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# of value changed.
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write_to_memory(CH0_HIGH_WORD_ADDR, high_word)
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write_to_memory(CH0_LOW_WORD_ADDR, low_word)
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write_to_memory(CH1_HIGH_WORD_ADDR, high_word)
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write_to_memory(CH1_LOW_WORD_ADDR, low_word)
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print(f"Set DAC Input Override Value to: 0x{value:04X}")
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def check_clk_relationship(spi):
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# Trigger the retimer to reacquire the clock relationship
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spi_write(spi, 0x14, 0x00)
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spi_write(spi, 0x14, 0x08)
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spi_write(spi, 0x14, 0x00)
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clkmode_reg = spi_read(spi, 0x14)
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print(f"AD9117 CLKMODE reg: 0x{clkmode_reg:02X}")
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if clkmode_reg & 0b00010000:
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print("Ad9117 Clock relationship is established")
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return False
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else:
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print("Ad9117 Clock relationship is found")
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return True
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def configure_ad9117():
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print()
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print("### Initializing AD9117 Dac")
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success = True
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spi = spidev.SpiDev()
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spi.open(MAIN_DAC_BUS, MAIN_DAC_DEVICE)
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spi.max_speed_hz = 5000
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spi.mode = 0b00 # CPOL = 0 CPHA = 0
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spi.cshigh = False
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try:
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soft_reset(spi)
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if not check_version(spi):
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print("Unrecognized DAC version")
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return False
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# Disable DAC Output during Initialization
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spi_write(spi, 0x01, 0x46)
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success &= verify_registers_vals(spi, {0x01: 0x46})
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success &= configure_dac(spi)
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success &= check_clk_relationship(spi)
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success &= dac_self_calibration(spi)
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power_down_afe(0, False)
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power_down_afe(1, False)
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if success:
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set_dac_input_override(False)
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# Re-Enable DAC Output
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spi_write(spi, 0x01, 0x40)
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verify_registers_vals(spi, {0x01: 0x40})
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print("AD9117 Dac init completed")
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else:
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print("AD9117 Dac init fails")
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return success
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except Exception as e:
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print(f"Error configuring AD9117 Dac: {e}")
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return False
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finally:
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spi.close()
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if __name__ == "__main__":
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configure_ad9117() |