forked from M-Labs/nix-servo
linuswck
90f18a2a00
- Si5340 should be initialized first before calling any PL register since if
Si5340 is not preprogrammed, there is not PL system clock driving any PL register.
- Adc Initialization causes the PL MMCM to relock and trigger a global PL reset. Thus,
CSR registers should only be altered after Adc is initialized successfully.
182 lines
6.0 KiB
Python
182 lines
6.0 KiB
Python
# This file is part of Fast Servo Software Package.
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#
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# Copyright (C) 2023 Jakub Matyas
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# Warsaw University of Technology <jakubk.m@gmail.com>
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# SPDX-License-Identifier: GPL-3.0-or-later
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#
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# This program is free software: you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation, either version 3 of the License, or
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# (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program. If not, see <https://www.gnu.org/licenses/>.
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import time
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import spidev
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from pyfastservo.common import (
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ADC_AFE_CTRL_ADDR,
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ADC_BITSLIP_ADDR,
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ADC_CH0_HIGH_ADDR,
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ADC_CH0_LOW_ADDR,
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ADC_CH1_HIGH_ADDR,
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ADC_CH1_LOW_ADDR,
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ADC_DELAY_ADDR,
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ADC_FRAME_ADDR,
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AUX_ADC_ADDR,
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MAP_MASK,
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PAGESIZE,
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write_to_memory,
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read_from_memory
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)
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# /dev/spidev1.0 <=> spidev<BUS>.<DEVICE>
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MAIN_ADC_BUS = 1
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MAIN_ADC_DEVICE = 1
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AUX_ADC_BUS = 1
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AUX_ADC_PORT_A = 2
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AUX_ADC_PORT_B = 3
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def spi_write(spi, address, value):
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spi.xfer2([address, value])
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def spi_read(spi, address):
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rx_buffer = spi.xfer2([0x80 | address, 0x00])
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return rx_buffer[1]
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def main_adc_config(spi, test_pattern):
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high_word = (test_pattern & 0xFF00) >> 8
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low_word = test_pattern & 0xFF
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register_settings = {
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0x01: 0x20, # REGISTER A1: set to Two's complement Data Format
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0x02: 0x11, # REGISTER A2: set to LVDS output, set 4 data lanes
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0x03: high_word, # REGISTER A3: test pattern high word
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0x04: low_word, # REGISTER A4: test pattern low word
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}
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spi_write(spi, 0x00, 0x80) # Soft Reset
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for addr, val in register_settings.items():
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spi_write(spi, addr, val)
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return verify_registers_vals(spi, register_settings)
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def main_adc_test_mode(spi, enable):
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value = spi_read(spi, 0x02)
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# set to LVDS output, set 4 data lanes and turn on or off test mode
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if enable:
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value |= 1 << 2
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else:
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value &= 0xfb
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spi_write(spi, 0x02, value)
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return verify_registers_vals(spi, {0x02: value})
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def verify_registers_vals(spi, reg_to_check):
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for register, expected_value in reg_to_check.items():
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value = spi_read(spi, register)
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if value != expected_value:
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print(f"Different value read than sent in reg 0x{register:02x}. Expected: 0x{expected_value:02x} Got: 0x{value:02x}")
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return False
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return True
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def read_frame():
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return read_from_memory(ADC_FRAME_ADDR, 1)[0]
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def perform_word_alignment():
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for i in range(4):
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current_frame = read_frame()
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if current_frame & 0x0F != 0x0C:
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print(f"Performing bitslip (iteration: {i}). Current frame: 0x{current_frame:02x}")
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write_to_memory(ADC_BITSLIP_ADDR, 1)
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else:
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print(f"No bitslip required; Current frame: 0x{current_frame:02x}")
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break
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prev_frame = read_frame()
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for tap_delay in range(32):
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write_to_memory(ADC_DELAY_ADDR, tap_delay)
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current_frame = read_frame()
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print(f"Tap delay: {tap_delay}, Current frame: 0x{current_frame:02x}")
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print(f"prev_frame: 0x{prev_frame:02x}")
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if current_frame != prev_frame:
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final_delay = ((tap_delay+1) // 2) + 2
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print(f"Edge detected; setting iDelay to: {final_delay}")
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write_to_memory(ADC_DELAY_ADDR, final_delay)
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return True
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prev_frame = current_frame
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return False
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def read_adc_channel(high_addr, low_addr):
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return (read_from_memory(high_addr, 1)[0] << 8) | read_from_memory(low_addr, 1)[0]
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def is_clk_aligned(spi, test_pattern):
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aligned = True
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main_adc_test_mode(spi, True)
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for i in range(100):
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adc_ch0 = read_adc_channel(ADC_CH0_HIGH_ADDR, ADC_CH0_LOW_ADDR)
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adc_ch1 = read_adc_channel(ADC_CH1_HIGH_ADDR, ADC_CH1_LOW_ADDR)
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if adc_ch0 != test_pattern or adc_ch1 != test_pattern:
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aligned = False
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break
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main_adc_test_mode(spi, False)
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return aligned
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def enable_adc_afe(ch1_x10=False, ch2_x10=False):
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ctrl_value = (ch2_x10 << 1) | ch1_x10
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write_to_memory(ADC_AFE_CTRL_ADDR, ctrl_value)
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afe_ctrl = read_from_memory(ADC_AFE_CTRL_ADDR, 1)[0]
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print(f"Configure ADC AFE Gain: ch1_10x: {"10x" if ch1_x10 else "1x"} | ch2_x10: {"10x" if ch2_x10 else "1x"}")
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return afe_ctrl
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def print_adc_channel(ch):
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if ch == 0:
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adc_ch0 = read_adc_channel(ADC_CH0_HIGH_ADDR, ADC_CH0_LOW_ADDR)
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print(f"Final ADC_CH0: 0x{adc_ch0:04x}")
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if ch == 1:
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adc_ch1 = read_adc_channel(ADC_CH1_HIGH_ADDR, ADC_CH1_LOW_ADDR)
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print(f"Final ADC_CH1: 0x{adc_ch1:04x}")
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def configure_ltc2195():
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# Calling this fn stops the PL input clock momentarily, triggers PL reset.
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print()
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print("### Initializing LTC2195 Adc")
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spi = spidev.SpiDev()
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spi.open(MAIN_ADC_BUS, MAIN_ADC_DEVICE)
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spi.max_speed_hz = 50000
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spi.mode = 0b00 # CPOL = 0 CPHA = 0
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spi.cshigh = False
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success = True
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try:
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test_pattern = 0x811F
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success &= main_adc_config(spi, test_pattern)
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success &= perform_word_alignment()
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if is_clk_aligned(spi, test_pattern):
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print("PL Data and Clock Alignment is verified")
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else:
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success &= False
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print("Error: Clocks are not aligned")
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enable_adc_afe(ch1_x10=0, ch2_x10=0)
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except Exception as e:
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print(f"Error configuring LTC2195: {e}")
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success = False
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finally:
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spi.close()
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if success:
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print("LTC2195 Adc init completed")
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else:
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print("LTC2195 Adc init failed")
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return success
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if __name__ == "__main__":
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configure_ltc2195() |