forked from M-Labs/nix-servo
180 lines
6.1 KiB
Python
180 lines
6.1 KiB
Python
# This file is part of Fast Servo Software Package.
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#
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# Copyright (C) 2023 Jakub Matyas
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# Warsaw University of Technology <jakubk.m@gmail.com>
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# SPDX-License-Identifier: GPL-3.0-or-later
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#
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# This program is free software: you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation, either version 3 of the License, or
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# (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program. If not, see <https://www.gnu.org/licenses/>.
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from migen import *
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from migen.genlib.cdc import MultiReg
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from misoc.interconnect.csr import AutoCSR, CSRStatus, CSRStorage
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class _CRG(Module):
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def __init__(self, platform, dco_clk, dco_freq=200e6):
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self.clock_domains.cd_dco = ClockDomain()
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self.clock_domains.cd_dco2x = ClockDomain()
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self.clock_domains.cd_dco2d = ClockDomain()
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dco_clk_p, dco_clk_n = dco_clk
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dco_clk_buf = Signal()
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self.specials += Instance(
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"IBUFGDS", i_I=dco_clk_p, i_IB=dco_clk_n, o_O=dco_clk_buf
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)
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# # #
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clk_feedback = Signal()
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clk_feedback_buf = Signal()
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clk_dco = Signal()
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clk_dco2x = Signal()
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clk_dco2d = Signal()
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self.locked = Signal()
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platform.add_period_constraint(dco_clk_p, 1e9 / dco_freq)
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self.specials += [
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Instance(
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"PLLE2_BASE",
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p_BANDWIDTH="OPTIMIZED",
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p_DIVCLK_DIVIDE=1,
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p_CLKFBOUT_PHASE=0.0,
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p_CLKFBOUT_MULT=4, # VCO @ 800 MHz
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p_CLKIN1_PERIOD=(1e9 / dco_freq),
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p_REF_JITTER1=0.01,
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p_STARTUP_WAIT="FALSE",
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i_CLKIN1=dco_clk_buf,
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i_PWRDWN=0,
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i_RST=ResetSignal("sys"),
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i_CLKFBIN=clk_feedback_buf,
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o_CLKFBOUT=clk_feedback,
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p_CLKOUT0_DIVIDE=4,
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p_CLKOUT0_PHASE=0.0,
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p_CLKOUT0_DUTY_CYCLE=0.5,
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o_CLKOUT0=clk_dco, # 200 MHz <- dco_clk
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p_CLKOUT1_DIVIDE=2,
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p_CLKOUT1_PHASE=0.0,
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p_CLKOUT1_DUTY_CYCLE=0.5,
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o_CLKOUT1=clk_dco2x, # 400 MHZ <- 2 * dco_clk = 2*200 MHz
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p_CLKOUT2_DIVIDE=8,
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p_CLKOUT2_PHASE=0.0,
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p_CLKOUT2_DUTY_CYCLE=0.5,
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o_CLKOUT2=clk_dco2d, # 100 MHz <- dco_clk / 2 = 200 MHz / 2
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o_LOCKED=self.locked,
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)
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]
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self.specials += Instance("BUFG", i_I=clk_feedback, o_O=clk_feedback_buf)
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self.specials += Instance("BUFG", i_I=clk_dco, o_O=self.cd_dco.clk)
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self.specials += Instance("BUFG", i_I=clk_dco2d, o_O=self.cd_dco2d.clk)
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self.specials += Instance("BUFG", i_I=clk_dco2x, o_O=self.cd_dco2x.clk)
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class ADC(Module, AutoCSR):
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def __init__(self, platform, dco_freq=200e6):
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adc_pads = platform.request("adc")
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afe_pads = platform.request("adc_afe")
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self.frame_csr = CSRStatus(4)
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self.data_ch0 = CSRStatus(16)
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self.data_ch1 = CSRStatus(16)
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self.tap_delay = CSRStorage(5)
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self.bitslip_csr = CSRStorage(1)
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self.afe_ctrl = CSRStorage(4)
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tap_delay_val = Signal(5)
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bitslip = Signal()
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bitslip_re_dco_2d = Signal()
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ch1_gain_x10 = Signal()
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ch2_gain_x10 = Signal()
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ch1_shdn = Signal()
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ch2_shdn = Signal()
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self.data_out = [Signal(16, reset_less=True), Signal(16, reset_less=True)]
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self.s_frame = Signal(4)
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###
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# DCO clock coming from LTC2195
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# dco_clk = Record([("p", 1), ("n", 1)])
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dco_clk =(adc_pads.dco_p, adc_pads.dco_n)
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self.comb += [
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# dco_clk.p.eq(adc_pads.dco_p),
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# dco_clk.n.eq(adc_pads.dco_n),
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tap_delay_val.eq(self.tap_delay.storage),
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Cat(ch1_gain_x10, ch2_gain_x10, ch1_shdn, ch2_shdn).eq(
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self.afe_ctrl.storage
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),
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]
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self.submodules._crg = _CRG(platform, dco_clk, dco_freq)
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self.specials += MultiReg(self.bitslip_csr.re, bitslip_re_dco_2d, "dco2d")
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self.sync.dco2d += [
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bitslip.eq(Mux(bitslip_re_dco_2d, self.bitslip_csr.storage, 0))
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]
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self.comb += [
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self.frame_csr.status.eq(self.s_frame),
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self.data_ch0.status.eq(self.data_out[0]),
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self.data_ch1.status.eq(self.data_out[1]),
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]
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self.comb += [
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afe_pads.ch1_gain.eq(ch1_gain_x10),
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afe_pads.ch2_gain.eq(ch2_gain_x10),
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afe_pads.nshdn_ch1.eq(~ch1_shdn),
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afe_pads.nshdn_ch2.eq(~ch2_shdn),
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]
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dummy = Signal(8)
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dummy_idelay_rdy = Signal()
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self.specials += Instance(
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"LTC2195",
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i_rst_in=ResetSignal("sys"),
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i_clk200=ClockSignal("idelay"),
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i_DCO=ClockSignal("dco"),
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i_DCO_2D=ClockSignal("dco2d"),
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i_FR_in_p=adc_pads.frame_p,
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i_FR_in_n=adc_pads.frame_n,
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i_D0_in_p=adc_pads.data0_p,
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i_D0_in_n=adc_pads.data0_n,
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i_D1_in_p=adc_pads.data1_p,
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i_D1_in_n=adc_pads.data1_n,
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i_bitslip=bitslip,
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i_delay_val=tap_delay_val,
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o_ADC0_out=self.data_out[1], # LANES swapped on hardware
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o_ADC1_out=self.data_out[0],
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o_FR_out=self.s_frame,
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o_o_data_from_pins=dummy,
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o_idelay_rdy=dummy_idelay_rdy,
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)
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class AUX_ADC_CTRL(Module, AutoCSR):
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def __init__(self, platform):
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adc_aux_pads = platform.request("aux_adc")
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self.adc_aux_ctrl = CSRStorage(5)
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self.comb += [
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adc_aux_pads.diff_n.eq(~self.adc_aux_ctrl.storage[0]),
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adc_aux_pads.a.eq(self.adc_aux_ctrl.storage[1:4]),
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adc_aux_pads.range.eq(self.adc_aux_ctrl.storage[4]),
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]
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