# diff from elhep/Fast-Servo-Firmmware commit ID 7fae40c:
# https://github.com/elhep/Fast-Servo-Firmware/commit/7fae40c0f872a91218be378f8289b98b1e366729
# Fix for migen add_source deprecation and removed xilinx bootgen command
# .bin file is being generated by bit2bin.py from Linien repository
# https://github.com/linien-org/linien/blob/master/gateware/bit2bin.py 

diff --git a/fast_servo/gateware/fast_servo_platform.py b/fast_servo/gateware/fast_servo_platform.py
index 13b4aa3..89a8103 100644
--- a/fast_servo/gateware/fast_servo_platform.py
+++ b/fast_servo/gateware/fast_servo_platform.py
@@ -324,7 +324,12 @@ class Platform(XilinxPlatform):
         self.ps7_config = ps7_config
 
         verilog_sources = os.listdir(verilog_dir)
-        self.add_sources(verilog_dir, *verilog_sources)
+        self.add_source_dir(verilog_dir)
+
+    def build(self, *args, **kwargs):
+        build_dir = kwargs.get('build_dir', 'build')
+        self.copy_sources(build_dir)
+        super().build(*args, **kwargs)
 
     def do_finalize(self, fragment):
         try:
diff --git a/fast_servo/gateware/fast_servo_soc.py b/fast_servo/gateware/fast_servo_soc.py
index 02128f5..abfc583 100644
--- a/fast_servo/gateware/fast_servo_soc.py
+++ b/fast_servo/gateware/fast_servo_soc.py
@@ -282,9 +282,3 @@ if __name__ == "__main__":
     os.chdir(os.path.join(root_path, build_dir))
     with open(f"{build_name}.bif", "w") as f:
         f.write(f"all:\n{{\n\t{build_name}.bit\n}}")
-    
-    cmd = f"bootgen -image {build_name}.bif -arch zynq -process_bitstream bin -w on".split(" ")
-    subprocess.run(cmd)
-
-    
-