flake: update dependencies

- Fix Painter path exceeds +/-32767 pixels bug
- Plotting with OpenGL has worse performance
    - See pyqtgraph Issue #2227

README.md

@@ -16,6 +16,15 @@
     - MODE: ON
 2. Install the SD Card, power up the board via the power jack or PoE and plug in the RJ45 Ethernet cable.
 3. Wait for all the front panel LEDs except the termination status LEDs to turn off. It can take a minutes or two for first boot. If it does not boot up, try to flash the SD Card again.
-4. Run `ssh <fast servo ip address> -p 3030` to ssh into fast-servo and run `linien-server run` to start the linien server.
+4. By default, linien-server starts up automatically. In case linien-server crashes, it will restart itself. Logs are stored in `/root/linien-server-log`. Here are some commands to interact with the linien-server service once you `ssh <fast servo ip address> -p 3030` into fast-servo.
-5. In the dev shell, run `linien` to launch the GUI. Add new device. Username is `root` and it does not take any password to log in. You leave the password field with any text.
+
-6. Select the newly added device and click connect in the GUI to connect and start the GUI.
+| Description                                          | Command                                 |
+|------------------------------------------------------|-----------------------------------------|
+| Start the linien-server service                      | `linien-server start`                   |
+| Stop the linien-server service                       | `linien-server stop`                    |
+| Check if the linien-server service is running        | `linien-server status`                  |
+| Set the linien-server service to start at bootup     | `linien-server enable`                  |
+| Set the linien-server service not to start at bootup | `linien-server disable`                 |
+
+4. In the dev shell, run `linien` to launch the GUI. Add new device. Username is `root` and it does not take any password to log in. You leave the password field with any text.
+5. Select the newly added device and click connect in the GUI to connect and start the GUI.

fast-servo/fast-servo.dts

@@ -576,7 +576,7 @@
 / {
  cpus {
   cpu@0 {
-   operating-points = <500000 1000000 250000 1000000>;
+   operating-points = <666667 1000000 333334 1000000>;
   };
  };
 };

fast-servo/fsbl-support/ps7_init.c

@@ -25,23 +25,23 @@ unsigned long ps7_pll_init_data_3_0[] = {
     // .. FINISH: SLCR SETTINGS
     // .. START: PLL SLCR REGISTERS
     // .. .. START: ARM PLL INIT
-    // .. .. PLL_RES = 0xc
+    // .. .. PLL_RES = 0x2
-    // .. .. ==> 0XF8000110[7:4] = 0x0000000CU
+    // .. .. ==> 0XF8000110[7:4] = 0x00000002U
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x000000C0U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
     // .. .. PLL_CP = 0x2
     // .. .. ==> 0XF8000110[11:8] = 0x00000002U
     // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
-    // .. .. LOCK_CNT = 0x145
+    // .. .. LOCK_CNT = 0xfa
-    // .. .. ==> 0XF8000110[21:12] = 0x00000145U
+    // .. .. ==> 0XF8000110[21:12] = 0x000000FAU
-    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00145000U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x000FA000U
     // .. .. 
-    EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x001452C0U),
+    EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U),
     // .. .. .. START: UPDATE FB_DIV
-    // .. .. .. PLL_FDIV = 0x1e
+    // .. .. .. PLL_FDIV = 0x28
-    // .. .. .. ==> 0XF8000100[18:12] = 0x0000001EU
+    // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U
-    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x0001E000U
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00028000U
     // .. .. .. 
-    EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x0001E000U),
+    EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U),
     // .. .. .. FINISH: UPDATE FB_DIV
     // .. .. .. START: BY PASS PLL
     // .. .. .. PLL_BYPASS_FORCE = 1
@@ -273,9 +273,9 @@ unsigned long ps7_clock_init_data_3_0[] = {
     // .. CLKACT = 0x1
     // .. ==> 0XF8000140[0:0] = 0x00000001U
     // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. SRCSEL = 0x2
+    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000140[6:4] = 0x00000002U
+    // .. ==> 0XF8000140[6:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000070U    VAL : 0x00000020U
+    // ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
     // .. DIVISOR = 0x8
     // .. ==> 0XF8000140[13:8] = 0x00000008U
     // ..     ==> MASK : 0x00003F00U    VAL : 0x00000800U
@@ -283,7 +283,7 @@ unsigned long ps7_clock_init_data_3_0[] = {
     // .. ==> 0XF8000140[25:20] = 0x00000001U
     // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
     // .. 
-    EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00100821U),
+    EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00100801U),
     // .. CLKACT = 0x1
     // .. ==> 0XF800014C[0:0] = 0x00000001U
     // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
@@ -4054,23 +4054,23 @@ unsigned long ps7_pll_init_data_2_0[] = {
     // .. FINISH: SLCR SETTINGS
     // .. START: PLL SLCR REGISTERS
     // .. .. START: ARM PLL INIT
-    // .. .. PLL_RES = 0xc
+    // .. .. PLL_RES = 0x2
-    // .. .. ==> 0XF8000110[7:4] = 0x0000000CU
+    // .. .. ==> 0XF8000110[7:4] = 0x00000002U
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x000000C0U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
     // .. .. PLL_CP = 0x2
     // .. .. ==> 0XF8000110[11:8] = 0x00000002U
     // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
-    // .. .. LOCK_CNT = 0x145
+    // .. .. LOCK_CNT = 0xfa
-    // .. .. ==> 0XF8000110[21:12] = 0x00000145U
+    // .. .. ==> 0XF8000110[21:12] = 0x000000FAU
-    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00145000U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x000FA000U
     // .. .. 
-    EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x001452C0U),
+    EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U),
     // .. .. .. START: UPDATE FB_DIV
-    // .. .. .. PLL_FDIV = 0x1e
+    // .. .. .. PLL_FDIV = 0x28
-    // .. .. .. ==> 0XF8000100[18:12] = 0x0000001EU
+    // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U
-    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x0001E000U
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00028000U
     // .. .. .. 
-    EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x0001E000U),
+    EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U),
     // .. .. .. FINISH: UPDATE FB_DIV
     // .. .. .. START: BY PASS PLL
     // .. .. .. PLL_BYPASS_FORCE = 1
@@ -4302,9 +4302,9 @@ unsigned long ps7_clock_init_data_2_0[] = {
     // .. CLKACT = 0x1
     // .. ==> 0XF8000140[0:0] = 0x00000001U
     // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. SRCSEL = 0x2
+    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000140[6:4] = 0x00000002U
+    // .. ==> 0XF8000140[6:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000070U    VAL : 0x00000020U
+    // ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
     // .. DIVISOR = 0x8
     // .. ==> 0XF8000140[13:8] = 0x00000008U
     // ..     ==> MASK : 0x00003F00U    VAL : 0x00000800U
@@ -4312,7 +4312,7 @@ unsigned long ps7_clock_init_data_2_0[] = {
     // .. ==> 0XF8000140[25:20] = 0x00000001U
     // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
     // .. 
-    EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00100821U),
+    EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00100801U),
     // .. CLKACT = 0x1
     // .. ==> 0XF800014C[0:0] = 0x00000001U
     // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
@@ -8236,23 +8236,23 @@ unsigned long ps7_pll_init_data_1_0[] = {
     // .. FINISH: SLCR SETTINGS
     // .. START: PLL SLCR REGISTERS
     // .. .. START: ARM PLL INIT
-    // .. .. PLL_RES = 0xc
+    // .. .. PLL_RES = 0x2
-    // .. .. ==> 0XF8000110[7:4] = 0x0000000CU
+    // .. .. ==> 0XF8000110[7:4] = 0x00000002U
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x000000C0U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
     // .. .. PLL_CP = 0x2
     // .. .. ==> 0XF8000110[11:8] = 0x00000002U
     // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
-    // .. .. LOCK_CNT = 0x145
+    // .. .. LOCK_CNT = 0xfa
-    // .. .. ==> 0XF8000110[21:12] = 0x00000145U
+    // .. .. ==> 0XF8000110[21:12] = 0x000000FAU
-    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00145000U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x000FA000U
     // .. .. 
-    EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x001452C0U),
+    EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U),
     // .. .. .. START: UPDATE FB_DIV
-    // .. .. .. PLL_FDIV = 0x1e
+    // .. .. .. PLL_FDIV = 0x28
-    // .. .. .. ==> 0XF8000100[18:12] = 0x0000001EU
+    // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U
-    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x0001E000U
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00028000U
     // .. .. .. 
-    EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x0001E000U),
+    EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U),
     // .. .. .. FINISH: UPDATE FB_DIV
     // .. .. .. START: BY PASS PLL
     // .. .. .. PLL_BYPASS_FORCE = 1
@@ -8484,9 +8484,9 @@ unsigned long ps7_clock_init_data_1_0[] = {
     // .. CLKACT = 0x1
     // .. ==> 0XF8000140[0:0] = 0x00000001U
     // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. SRCSEL = 0x2
+    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000140[6:4] = 0x00000002U
+    // .. ==> 0XF8000140[6:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000070U    VAL : 0x00000020U
+    // ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
     // .. DIVISOR = 0x8
     // .. ==> 0XF8000140[13:8] = 0x00000008U
     // ..     ==> MASK : 0x00003F00U    VAL : 0x00000800U
@@ -8494,7 +8494,7 @@ unsigned long ps7_clock_init_data_1_0[] = {
     // .. ==> 0XF8000140[25:20] = 0x00000001U
     // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
     // .. 
-    EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00100821U),
+    EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00100801U),
     // .. CLKACT = 0x1
     // .. ==> 0XF800014C[0:0] = 0x00000001U
     // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U

fast-servo/fsbl-support/ps7_init_gpl.c

@@ -38,23 +38,23 @@ unsigned long ps7_pll_init_data_3_0[] = {
     // .. FINISH: SLCR SETTINGS
     // .. START: PLL SLCR REGISTERS
     // .. .. START: ARM PLL INIT
-    // .. .. PLL_RES = 0xc
+    // .. .. PLL_RES = 0x2
-    // .. .. ==> 0XF8000110[7:4] = 0x0000000CU
+    // .. .. ==> 0XF8000110[7:4] = 0x00000002U
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x000000C0U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
     // .. .. PLL_CP = 0x2
     // .. .. ==> 0XF8000110[11:8] = 0x00000002U
     // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
-    // .. .. LOCK_CNT = 0x145
+    // .. .. LOCK_CNT = 0xfa
-    // .. .. ==> 0XF8000110[21:12] = 0x00000145U
+    // .. .. ==> 0XF8000110[21:12] = 0x000000FAU
-    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00145000U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x000FA000U
     // .. .. 
-    EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x001452C0U),
+    EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U),
     // .. .. .. START: UPDATE FB_DIV
-    // .. .. .. PLL_FDIV = 0x1e
+    // .. .. .. PLL_FDIV = 0x28
-    // .. .. .. ==> 0XF8000100[18:12] = 0x0000001EU
+    // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U
-    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x0001E000U
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00028000U
     // .. .. .. 
-    EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x0001E000U),
+    EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U),
     // .. .. .. FINISH: UPDATE FB_DIV
     // .. .. .. START: BY PASS PLL
     // .. .. .. PLL_BYPASS_FORCE = 1
@@ -286,9 +286,9 @@ unsigned long ps7_clock_init_data_3_0[] = {
     // .. CLKACT = 0x1
     // .. ==> 0XF8000140[0:0] = 0x00000001U
     // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. SRCSEL = 0x2
+    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000140[6:4] = 0x00000002U
+    // .. ==> 0XF8000140[6:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000070U    VAL : 0x00000020U
+    // ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
     // .. DIVISOR = 0x8
     // .. ==> 0XF8000140[13:8] = 0x00000008U
     // ..     ==> MASK : 0x00003F00U    VAL : 0x00000800U
@@ -296,7 +296,7 @@ unsigned long ps7_clock_init_data_3_0[] = {
     // .. ==> 0XF8000140[25:20] = 0x00000001U
     // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
     // .. 
-    EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00100821U),
+    EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00100801U),
     // .. CLKACT = 0x1
     // .. ==> 0XF800014C[0:0] = 0x00000001U
     // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
@@ -4067,23 +4067,23 @@ unsigned long ps7_pll_init_data_2_0[] = {
     // .. FINISH: SLCR SETTINGS
     // .. START: PLL SLCR REGISTERS
     // .. .. START: ARM PLL INIT
-    // .. .. PLL_RES = 0xc
+    // .. .. PLL_RES = 0x2
-    // .. .. ==> 0XF8000110[7:4] = 0x0000000CU
+    // .. .. ==> 0XF8000110[7:4] = 0x00000002U
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x000000C0U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
     // .. .. PLL_CP = 0x2
     // .. .. ==> 0XF8000110[11:8] = 0x00000002U
     // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
-    // .. .. LOCK_CNT = 0x145
+    // .. .. LOCK_CNT = 0xfa
-    // .. .. ==> 0XF8000110[21:12] = 0x00000145U
+    // .. .. ==> 0XF8000110[21:12] = 0x000000FAU
-    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00145000U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x000FA000U
     // .. .. 
-    EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x001452C0U),
+    EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U),
     // .. .. .. START: UPDATE FB_DIV
-    // .. .. .. PLL_FDIV = 0x1e
+    // .. .. .. PLL_FDIV = 0x28
-    // .. .. .. ==> 0XF8000100[18:12] = 0x0000001EU
+    // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U
-    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x0001E000U
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00028000U
     // .. .. .. 
-    EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x0001E000U),
+    EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U),
     // .. .. .. FINISH: UPDATE FB_DIV
     // .. .. .. START: BY PASS PLL
     // .. .. .. PLL_BYPASS_FORCE = 1
@@ -4315,9 +4315,9 @@ unsigned long ps7_clock_init_data_2_0[] = {
     // .. CLKACT = 0x1
     // .. ==> 0XF8000140[0:0] = 0x00000001U
     // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. SRCSEL = 0x2
+    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000140[6:4] = 0x00000002U
+    // .. ==> 0XF8000140[6:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000070U    VAL : 0x00000020U
+    // ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
     // .. DIVISOR = 0x8
     // .. ==> 0XF8000140[13:8] = 0x00000008U
     // ..     ==> MASK : 0x00003F00U    VAL : 0x00000800U
@@ -4325,7 +4325,7 @@ unsigned long ps7_clock_init_data_2_0[] = {
     // .. ==> 0XF8000140[25:20] = 0x00000001U
     // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
     // .. 
-    EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00100821U),
+    EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00100801U),
     // .. CLKACT = 0x1
     // .. ==> 0XF800014C[0:0] = 0x00000001U
     // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
@@ -8249,23 +8249,23 @@ unsigned long ps7_pll_init_data_1_0[] = {
     // .. FINISH: SLCR SETTINGS
     // .. START: PLL SLCR REGISTERS
     // .. .. START: ARM PLL INIT
-    // .. .. PLL_RES = 0xc
+    // .. .. PLL_RES = 0x2
-    // .. .. ==> 0XF8000110[7:4] = 0x0000000CU
+    // .. .. ==> 0XF8000110[7:4] = 0x00000002U
-    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x000000C0U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
     // .. .. PLL_CP = 0x2
     // .. .. ==> 0XF8000110[11:8] = 0x00000002U
     // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
-    // .. .. LOCK_CNT = 0x145
+    // .. .. LOCK_CNT = 0xfa
-    // .. .. ==> 0XF8000110[21:12] = 0x00000145U
+    // .. .. ==> 0XF8000110[21:12] = 0x000000FAU
-    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00145000U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x000FA000U
     // .. .. 
-    EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x001452C0U),
+    EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U),
     // .. .. .. START: UPDATE FB_DIV
-    // .. .. .. PLL_FDIV = 0x1e
+    // .. .. .. PLL_FDIV = 0x28
-    // .. .. .. ==> 0XF8000100[18:12] = 0x0000001EU
+    // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U
-    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x0001E000U
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00028000U
     // .. .. .. 
-    EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x0001E000U),
+    EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U),
     // .. .. .. FINISH: UPDATE FB_DIV
     // .. .. .. START: BY PASS PLL
     // .. .. .. PLL_BYPASS_FORCE = 1
@@ -8497,9 +8497,9 @@ unsigned long ps7_clock_init_data_1_0[] = {
     // .. CLKACT = 0x1
     // .. ==> 0XF8000140[0:0] = 0x00000001U
     // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
-    // .. SRCSEL = 0x2
+    // .. SRCSEL = 0x0
-    // .. ==> 0XF8000140[6:4] = 0x00000002U
+    // .. ==> 0XF8000140[6:4] = 0x00000000U
-    // ..     ==> MASK : 0x00000070U    VAL : 0x00000020U
+    // ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
     // .. DIVISOR = 0x8
     // .. ==> 0XF8000140[13:8] = 0x00000008U
     // ..     ==> MASK : 0x00003F00U    VAL : 0x00000800U
@@ -8507,7 +8507,7 @@ unsigned long ps7_clock_init_data_1_0[] = {
     // .. ==> 0XF8000140[25:20] = 0x00000001U
     // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
     // .. 
-    EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00100821U),
+    EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00100801U),
     // .. CLKACT = 0x1
     // .. ==> 0XF800014C[0:0] = 0x00000001U
     // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U

fast-servo/fsbl.patch

@@ -1,14 +1,8 @@
-diff --git a/lib/sw_apps/zynq_fsbl/misc/fast-servo/ps7_init.h b/lib/sw_apps/zynq_fsbl/misc/fast-servo/ps7_init.h
+diff --git a/lib/sw_apps/zynq_fsbl/misc/zc706/ps7_init.h b/lib/sw_apps/zynq_fsbl/misc/zc706/ps7_init.h
-index 9572636306..2f3816271e 100644
+index 9572636..1d79314 100644
---- a/lib/sw_apps/zynq_fsbl/misc/fast-servo/ps7_init.h
+--- a/lib/sw_apps/zynq_fsbl/misc/zc706/ps7_init.h
-+++ b/lib/sw_apps/zynq_fsbl/misc/fast-servo/ps7_init.h
++++ b/lib/sw_apps/zynq_fsbl/misc/zc706/ps7_init.h
-@@ -67,20 +67,20 @@ extern unsigned long  * ps7_peripherals_init_data;
+@@ -72,20 +72,20 @@ extern unsigned long  * ps7_peripherals_init_data;
- 
- /* Freq of all peripherals */
- 
--#define APU_FREQ  666666687
-+#define APU_FREQ  500000000
- #define DDR_FREQ  533333374
  #define DCI_FREQ  10158730
  #define QSPI_FREQ  200000000
  #define SMC_FREQ  10000000
@@ -20,27 +14,25 @@ index 9572636306..2f3816271e 100644
 -#define SDIO_FREQ  50000000
 -#define UART_FREQ  50000000
 -#define SPI_FREQ  10000000
--#define I2C_FREQ  111111115
--#define WDT_FREQ  111111115
 +#define SDIO_FREQ  100000000
 +#define UART_FREQ  100000000
 +#define SPI_FREQ  166666672
-+#define I2C_FREQ  83333336
+ #define I2C_FREQ  111111115
-+#define WDT_FREQ  83333336
+ #define WDT_FREQ  111111115
  #define TTC_FREQ  50000000
  #define CAN_FREQ  10000000
  #define PCAP_FREQ  200000000
-diff --git a/lib/sw_apps/zynq_fsbl/misc/fast-servo/ps7_init_gpl.h b/lib/sw_apps/zynq_fsbl/misc/fast-servo/ps7_init_gpl.h
+ #define TPIU_FREQ  200000000
-index 8962bed427..df2f16adec 100644
+-#define FPGA0_FREQ  50000000
---- a/lib/sw_apps/zynq_fsbl/misc/fast-servo/ps7_init_gpl.h
++#define FPGA0_FREQ  10000000
-+++ b/lib/sw_apps/zynq_fsbl/misc/fast-servo/ps7_init_gpl.h
+ #define FPGA1_FREQ  10000000
-@@ -81,20 +81,20 @@ extern unsigned long  * ps7_peripherals_init_data;
+ #define FPGA2_FREQ  10000000
- 
+ #define FPGA3_FREQ  10000000
- /* Freq of all peripherals */
+diff --git a/lib/sw_apps/zynq_fsbl/misc/zc706/ps7_init_gpl.h b/lib/sw_apps/zynq_fsbl/misc/zc706/ps7_init_gpl.h
- 
+index 8962bed..562d5b5 100644
--#define APU_FREQ  666666687
+--- a/lib/sw_apps/zynq_fsbl/misc/zc706/ps7_init_gpl.h
-+#define APU_FREQ  500000000
++++ b/lib/sw_apps/zynq_fsbl/misc/zc706/ps7_init_gpl.h
- #define DDR_FREQ  533333374
+@@ -86,20 +86,20 @@ extern unsigned long  * ps7_peripherals_init_data;
  #define DCI_FREQ  10158730
  #define QSPI_FREQ  200000000
  #define SMC_FREQ  10000000
@@ -52,33 +44,37 @@ index 8962bed427..df2f16adec 100644
 -#define SDIO_FREQ  50000000
 -#define UART_FREQ  50000000
 -#define SPI_FREQ  10000000
--#define I2C_FREQ  111111115
--#define WDT_FREQ  111111115
 +#define SDIO_FREQ  100000000
 +#define UART_FREQ  100000000
 +#define SPI_FREQ  166666672
-+#define I2C_FREQ  83333336
+ #define I2C_FREQ  111111115
-+#define WDT_FREQ  83333336
+ #define WDT_FREQ  111111115
  #define TTC_FREQ  50000000
  #define CAN_FREQ  10000000
  #define PCAP_FREQ  200000000
+ #define TPIU_FREQ  200000000
+-#define FPGA0_FREQ  50000000
++#define FPGA0_FREQ  10000000
+ #define FPGA1_FREQ  10000000
+ #define FPGA2_FREQ  10000000
+ #define FPGA3_FREQ  10000000
 diff --git a/lib/sw_apps/zynq_fsbl/misc/fast-servo/xparameters.h b/lib/sw_apps/zynq_fsbl/misc/fast-servo/xparameters.h
 index 997a982ca1..5461fbb477 100644
---- a/lib/sw_apps/zynq_fsbl/misc/fast-servo/xparameters.h
+--- a/lib/sw_apps/zynq_fsbl/misc/fast-servo/xparameters 
 +++ b/lib/sw_apps/zynq_fsbl/misc/fast-servo/xparameters.h
 @@ -9,21 +9,26 @@
  #define XPAR_CPU_ID 0U
  
  /* Definitions for peripheral PS7_CORTEXA9_0 */
 -#define XPAR_PS7_CORTEXA9_0_CPU_CLK_FREQ_HZ 666666687
-+#define XPAR_PS7_CORTEXA9_0_CPU_CLK_FREQ_HZ 500000000
++#define XPAR_PS7_CORTEXA9_0_CPU_CLK_FREQ_HZ 666666687
  
  
  /******************************************************************/
  
  /* Canonical definitions for peripheral PS7_CORTEXA9_0 */
 -#define XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ 666666687
-+#define XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ 500000000
++#define XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ 666666687
  
  
  /******************************************************************/

fast-servo/iir_pipeline.patch

@@ -1,13 +0,0 @@
-diff --git a/gateware/logic/iir.py b/gateware/logic/iir.py
-index 2380dd7..60bfeb7 100644
---- a/gateware/logic/iir.py
-+++ b/gateware/logic/iir.py
-@@ -89,7 +89,7 @@ class Iir(Filter):
-                 zr = Signal.like(z)
-                 self.sync += zr.eq(z)
-                 z = Signal.like(zr)
--                self.comb += z.eq(zr + signal * c[coeff])
-+                self.sync += z.eq(zr + signal * c[coeff])
-             self.comb += y_next.eq(z)
-             self.latency.value = Constant(order + 1)
-             self.interval.value = Constant(1)

fast-servo/linien-common-fast-servo-hardware-specific.patch

@@ -8,8 +8,8 @@ index 854d776..a310dbe 100644
  
 -MHz = 0x10000000 / 8
 -Vpp = ((1 << 14) - 1) / 4
-+MHz = 0x10000000 / 8 * 125 / 100
++MHz = 0x10000000 / 8
-+Vpp = (1 << 14) * 0.5 / 0.425 - 1
++Vpp = (1 << 14 - 1) / 0.355 * 0.85
  # conversion of bits to V
  ANALOG_OUT_V = 1.8 / ((2**15) - 1)
  

fast-servo/linien-demodulate_add_pipeline.patch

@@ -0,0 +1,21 @@
+diff --git a/gateware/logic/modulate.py b/gateware/logic/modulate.py
+index c750306..ffba1b2 100644
+--- a/gateware/logic/modulate.py
++++ b/gateware/logic/modulate.py
+@@ -45,12 +45,14 @@ class Demodulate(Module, AutoCSR):
+             cordic_mode="rotate",
+             func_mode="circular",
+         )
+-        self.comb += [
++        self.sync += [
+             # cordic input
+             self.cordic.xi.eq(self.x),
+             self.cordic.zi.eq(
+                 ((self.phase * self.multiplier.storage) + self.delay.storage) << 1
+-            ),
++            )
++        ]
++        self.comb += [
+             # cordic output
+             self.i.eq(self.cordic.xo >> 1),
+             self.q.eq(self.cordic.yo >> 1),

fast-servo/linien-gateware-autolock-pipeline.patch

@@ -1,5 +1,5 @@
 diff --git a/gateware/logic/autolock.py b/gateware/logic/autolock.py
-index a6dc764..1a8407f 100644
+index a6dc764..975b23f 100644
 --- a/gateware/logic/autolock.py
 +++ b/gateware/logic/autolock.py
 @@ -148,14 +148,17 @@ class RobustAutolock(Module, AutoCSR):
@@ -23,44 +23,66 @@ index a6dc764..1a8407f 100644
          ]
  
          # has this signal at the moment the same sign as the peak we are looking for?
-@@ -168,16 +171,17 @@ class RobustAutolock(Module, AutoCSR):
+@@ -167,36 +170,41 @@ class RobustAutolock(Module, AutoCSR):
+         # have we detected all peaks (and can turn on the lock)?
          all_instructions_triggered = Signal()
  
-         self.comb += [
+-        self.comb += [
 -            sign_equal.eq((sum_diff > 0) == (current_peak_height > 0)),
 -            If(sum_diff >= 0, abs_sum_diff.eq(sum_diff)).Else(
 -                abs_sum_diff.eq(-1 * sum_diff)
-+            sign_equal.eq((self.sum_diff > 0) == (current_peak_height > 0)),
+-            ),
-+            If(self.sum_diff >= 0, abs_sum_diff.eq(self.sum_diff)).Else(
+-            If(
-+                abs_sum_diff.eq(-1 * self.sum_diff)
+-                current_peak_height >= 0,
-             ),
++        self.sync += [
-             If(
++            If(current_peak_height >= 0, 
-                 current_peak_height >= 0,
                  abs_current_peak_height.eq(current_peak_height),
              ).Else(abs_current_peak_height.eq(-1 * current_peak_height)),
-             over_threshold.eq(abs_sum_diff >= abs_current_peak_height),
+-            over_threshold.eq(abs_sum_diff >= abs_current_peak_height),
 -            waited_long_enough.eq(waited_for > current_wait_for),
-+            # HACK: To compensate the lock position output for the pipeline delay
-+            waited_long_enough.eq((waited_for >= current_wait_for - 1) & (waited_for != 2 ** bits_for(N_points) - 1) & (current_wait_for - 1 != 2 ** bits_for(N_points) - 1)),
              all_instructions_triggered.eq(
                  self.current_instruction_idx >= self.N_instructions.storage
              ),
-@@ -190,7 +194,7 @@ class RobustAutolock(Module, AutoCSR):
++        ]
++        self.comb += [
++            sign_equal.eq((self.sum_diff > 0) == (current_peak_height > 0)),
++            If(self.sum_diff >= 0, abs_sum_diff.eq(self.sum_diff)).Else(
++                abs_sum_diff.eq(-1 * self.sum_diff)
++            ),
++            over_threshold.eq(abs_sum_diff >= abs_current_peak_height),
++            waited_long_enough.eq(waited_for > current_wait_for),
+             self.turn_on_lock.eq(
+                 all_instructions_triggered
+                 & (final_waited_for >= self.final_wait_time.storage)
+             ),
+         ]
+ 
++        watching_reg = Signal()
          self.sync += [
++            watching.eq(watching_reg),
              If(
                  self.at_start,
 -                waited_for.eq(0),
-+                waited_for.eq(-1),
++                # Compensate pipeline delay
++                waited_for.eq(1),
                  # fpga robust autolock algorithm registeres trigger events delayed.
                  # Therefore, we give it a head start for `final_waited_for`
                  final_waited_for.eq(ROBUST_AUTOLOCK_FPGA_DELAY),
-@@ -213,7 +217,8 @@ class RobustAutolock(Module, AutoCSR):
+                 self.current_instruction_idx.eq(0),
+-                If(self.request_lock, watching.eq(1)).Else(watching.eq(0)),
++                If(self.request_lock, watching_reg.eq(1)).Else(watching.eq(0), watching_reg.eq(0)),
+             ).Else(
++                # Compensate pipeline delay
+                 # not at start
+                 If(
+                     ~self.request_lock,
+@@ -213,7 +221,8 @@ class RobustAutolock(Module, AutoCSR):
                          self.current_instruction_idx.eq(
                              self.current_instruction_idx + 1
                          ),
 -                        waited_for.eq(0),
-+                        # HACK: To compensate the lock position output for the pipeline delay
++                        # Compensate pipeline delay
-+                        waited_for.eq(-1),
++                        waited_for.eq(1),
                      ).Else(waited_for.eq(waited_for + 1)),
                  ),
                  If(

fast-servo/linien-gateware-chain-pipeline.patch

@@ -0,0 +1,35 @@
+diff --git a/gateware/logic/chains.py b/gateware/logic/chains.py
+index a890849..3461a78 100644
+--- a/gateware/logic/chains.py
++++ b/gateware/logic/chains.py
+@@ -93,7 +93,6 @@ class FastChain(Module, AutoCSR):
+ 
+             self.comb += [
+                 x_limit.x.eq(([self.demod.i, self.demod.q][sub_channel_idx] << s) + dx),
+-                iir_c.x.eq(x_limit.y),
+                 iir_c.hold.eq(0),
+                 iir_c.clear.eq(0),
+                 iir_d.x.eq(iir_c.y),
+@@ -101,14 +100,20 @@ class FastChain(Module, AutoCSR):
+                 iir_d.clear.eq(0),
+             ]
+ 
++            self.sync += [
++                iir_c.x.eq(x_limit.y)
++            ]
++
+             ys = Array([iir_c.x, iir_c.y, iir_d.y])
+ 
+             output_signal_this_channel = (self.out_i, self.out_q)[sub_channel_idx]
+-            self.comb += [
++            self.sync += [
+                 y_limit.x.eq(
+                     Mux(self.invert.storage, -1, 1)
+                     * (ys[self.y_tap.storage] + (ya << s) + (offset_signal << s))
+-                ),
++                )
++            ]
++            self.comb += [
+                 output_signal_this_channel.eq(y_limit.y),
+             ]
+ 

fast-servo/linien-gateware/cores/adc.py

@@ -22,93 +22,8 @@ from migen.genlib.cdc import MultiReg
 from misoc.interconnect.csr import AutoCSR, CSRStatus, CSRStorage
 from misoc.interconnect.stream import AsyncFIFO
 
-
-class CRG(Module):
-    def __init__(self, platform, dco_clk, dco_freq=200e6):
-        self.clock_domains.cd_dco = ClockDomain()
-        self.clock_domains.cd_dco2x = ClockDomain()
-        self.clock_domains.cd_dco2d = ClockDomain()
-        self.clock_domains.cd_dco2d_45_degree = ClockDomain()
-        dco_clk_p, dco_clk_n = dco_clk
-
-        dco_clk_buf = Signal()
-        self.specials += Instance(
-            "IBUFGDS", i_I=dco_clk_p, i_IB=dco_clk_n, o_O=dco_clk_buf
-        )
-
-        # # #
-        clk_feedback = Signal()
-        clk_feedback_buf = Signal()
-
-        clk_dco = Signal()
-        clk_dco2x = Signal()
-        clk_dco2d = Signal()
-        clk_dco2d_45_degree = Signal()
-        mmcm_ps_psdone = Signal()
-
-        self.locked = Signal()
-        self.mmcm_rst = Signal()
-        self.ddr_clk_phase_shift_en = Signal()
-        self.ddr_clk_phase_incdec = Signal()
-
-        platform.add_period_constraint(dco_clk_p, 1e9 / dco_freq)
-        self.specials += [
-            Instance(
-                "MMCME2_ADV",
-                p_BANDWIDTH="OPTIMIZED",
-                p_DIVCLK_DIVIDE=1,
-                p_CLKFBOUT_PHASE=0.0,
-                p_CLKFBOUT_MULT_F=4,  # VCO @ 800 MHz
-                p_CLKIN1_PERIOD=(1e9 / dco_freq),
-                p_REF_JITTER1=0.01,
-                p_STARTUP_WAIT="FALSE",
-                i_CLKIN1=dco_clk_buf,
-                i_PWRDWN=0,
-                i_RST=ResetSignal("sys") | self.mmcm_rst,
-                i_CLKFBIN=clk_feedback_buf,
-                o_CLKFBOUT=clk_feedback,
-
-                p_CLKOUT0_USE_FINE_PS="TRUE",
-                p_CLKOUT0_DIVIDE_F=8,
-                p_CLKOUT0_PHASE=45.0,
-                p_CLKOUT0_DUTY_CYCLE=0.5,
-                o_CLKOUT0=clk_dco2d_45_degree,  # 100 MHz <- dco_clk / 2 = 200 MHz / 2
-                o_LOCKED=self.locked,
-
-                p_CLKOUT1_DIVIDE=2,
-                p_CLKOUT1_PHASE=0.0,
-                p_CLKOUT1_DUTY_CYCLE=0.5,
-                o_CLKOUT1=clk_dco2x,  # 400 MHZ <- 2 * dco_clk = 2*200 MHz
-                
-                p_CLKOUT2_DIVIDE=8,
-                p_CLKOUT2_PHASE=0.0,
-                p_CLKOUT2_DUTY_CYCLE=0.5,
-                o_CLKOUT2=clk_dco2d,  # 100 MHz <- dco_clk / 2 = 200 MHz / 2
-                
-                p_CLKOUT3_DIVIDE=4,
-                p_CLKOUT3_PHASE=0.0,
-                p_CLKOUT3_DUTY_CYCLE=0.5,
-                o_CLKOUT3=clk_dco,  # 200 MHz <- dco_clk
-
-                i_PSCLK=ClockSignal(),
-                i_PSEN=self.ddr_clk_phase_shift_en,
-                i_PSINCDEC=self.ddr_clk_phase_incdec,
-                o_PSDONE=mmcm_ps_psdone,
-            )
-        ]
-
-        self.specials += Instance("BUFG", i_I=clk_feedback, o_O=clk_feedback_buf)
-        self.specials += Instance("BUFG", i_I=clk_dco, o_O=self.cd_dco.clk)
-        self.specials += Instance("BUFG", i_I=clk_dco2d, o_O=self.cd_dco2d.clk)
-        self.specials += Instance("BUFG", i_I=clk_dco2d_45_degree, o_O=self.cd_dco2d_45_degree.clk)
-        self.specials += Instance("BUFG", i_I=clk_dco2x, o_O=self.cd_dco2x.clk)
-
-        # Ignore dco2d to mmcm dco_clk path created by SoC's rst.
-        platform.add_false_path_constraints(self.cd_dco2d.clk, dco_clk_buf)
-        self.specials += Instance("FD", p_INIT=1, i_D=~self.locked, i_C=self.cd_dco2d.clk, o_Q=self.cd_dco2d.rst)
-
 class ADC(Module, AutoCSR):
-    def __init__(self, platform, dco_freq=200e6):
+    def __init__(self, platform):
         adc_pads = platform.request("adc")
         afe_pads = platform.request("adc_afe")
 
@@ -131,45 +46,27 @@ class ADC(Module, AutoCSR):
         ch2_shdn = Signal()
 
         self.data_out = [Signal(16, reset_less=True), Signal(16, reset_less=True)]
-        self.data_out_cdc = [Signal(16, reset_less=True), Signal(16, reset_less=True)]
         self.s_frame = Signal(4)
-        self.s_frame_cdc = Signal(4)
 
-        self.submodules.cdc_fifo = ClockDomainsRenamer({"write": "dco2d", "read": "sys"})(AsyncFIFO([("data", 36)], 4))
         self.comb += [
-            self.cdc_fifo.sink.data.eq(Cat(self.data_out_cdc[0], self.data_out_cdc[1], self.s_frame_cdc)),
-            self.cdc_fifo.sink.stb.eq(~ResetSignal("dco2d")),
-            Cat(self.data_out[0], self.data_out[1], self.s_frame).eq(self.cdc_fifo.source.data),
-            self.cdc_fifo.source.ack.eq(~ResetSignal("sys")),
-        ]
-
-        ###
-
-        # DCO clock coming from LTC2195
-        # dco_clk = Record([("p", 1), ("n", 1)])
-        dco_clk =(adc_pads.dco_p, adc_pads.dco_n)
-        self.comb += [
-            # dco_clk.p.eq(adc_pads.dco_p),
-            # dco_clk.n.eq(adc_pads.dco_n),
             tap_delay_val.eq(self.tap_delay.storage),
             Cat(ch1_gain_x10, ch2_gain_x10, ch1_shdn, ch2_shdn).eq(
                 self.afe_ctrl.storage[0:4]
             ),
         ]
 
-        self.submodules.crg = CRG(platform, dco_clk, dco_freq)
+        # self.comb += self.afe_ctrl.storage[4].eq(self.crg.mmcm_rst)
-        self.comb += self.afe_ctrl.storage[4].eq(self.crg.mmcm_rst)
+        # self.comb += self.afe_ctrl.storage[5].eq(self.crg.ddr_clk_phase_shift_en)
-        self.comb += self.afe_ctrl.storage[5].eq(self.crg.ddr_clk_phase_shift_en)
+        # self.comb += self.afe_ctrl.storage[6].eq(self.crg.ddr_clk_phase_incdec)
-        self.comb += self.afe_ctrl.storage[6].eq(self.crg.ddr_clk_phase_incdec)
 
-        self.specials += MultiReg(self.bitslip_csr.re, bitslip_re_dco_2d, "dco2d")
+        self.specials += MultiReg(self.bitslip_csr.re, bitslip_re_dco_2d, "sys")
-        self.sync.dco2d += [
+        self.sync.sys += [
             bitslip.eq(Mux(bitslip_re_dco_2d, self.bitslip_csr.storage, 0))
         ]
 
         self.comb += [
             self.frame_csr.status[0:4].eq(self.s_frame[0:4]),
-            self.frame_csr.status[4].eq(self.crg.locked),
+            # self.frame_csr.status[4].eq(self.crg.locked),
             self.data_ch0.status.eq(self.data_out[0]),
             self.data_ch1.status.eq(self.data_out[1]),
         ]
@@ -186,10 +83,10 @@ class ADC(Module, AutoCSR):
 
         self.specials += Instance(
             "LTC2195",
-            i_rst_in=ResetSignal("dco2d"),
+            i_rst_in=ResetSignal("sys"),
             i_clk200=ClockSignal("idelay"),
-            i_DCO=ClockSignal("dco"),
+            i_DCO=ClockSignal("sys_double"),
-            i_DCO_2D=ClockSignal("dco2d"),
+            i_DCO_2D=ClockSignal("sys"),
             i_FR_in_p=adc_pads.frame_p,
             i_FR_in_n=adc_pads.frame_n,
             i_D0_in_p=adc_pads.data0_p,
@@ -198,9 +95,9 @@ class ADC(Module, AutoCSR):
             i_D1_in_n=adc_pads.data1_n,
             i_bitslip=bitslip,
             i_delay_val=tap_delay_val,
-            o_ADC0_out=self.data_out_cdc[1],        # LANES swapped on hardware
+            o_ADC0_out=self.data_out[1],        # LANES swapped on hardware
-            o_ADC1_out=self.data_out_cdc[0],
+            o_ADC1_out=self.data_out[0],
-            o_FR_out=self.s_frame_cdc,
+            o_FR_out=self.s_frame,
             o_o_data_from_pins=dummy,
             o_idelay_rdy=dummy_idelay_rdy,
         )

fast-servo/linien-gateware/cores/dac.py

@@ -24,10 +24,13 @@ from misoc.interconnect.stream import AsyncFIFO
 
 
 class DAC(Module, AutoCSR):
-    def __init__(self, platform):
+    def __init__(self, platform, phase_shift_ctrl):
         dac_pads = platform.request("dac")
         dac_afe_pads = platform.request("dac_afe")
-        self.dac_ctrl = CSRStorage(3)
+
+        phase_shift_en, phase_shift_dir = phase_shift_ctrl
+
+        self.dac_ctrl = CSRStorage(5)
         self.output_value_ch0 = CSRStorage(14)
         self.output_value_ch1 = CSRStorage(14)
 
@@ -40,46 +43,37 @@ class DAC(Module, AutoCSR):
 
         self.data_in = [Signal(14, reset_less=True), Signal(14, reset_less=True)]
         self.data_in_csr = [Signal(14, reset_less=True), Signal(14, reset_less=True)]
-        
-        self.data_in_cdc = [Signal(14, reset_less=True), Signal(14, reset_less=True)]
-        self.data_in_csr_cdc = [Signal(14, reset_less=True), Signal(14, reset_less=True)]
-        platform.add_period_constraint(dac_pads.dclkio, 10.0)
 
-        self.submodules.cdc_fifo = ClockDomainsRenamer({"write": "sys", "read": "dco2d"})(AsyncFIFO([("data", 56)], 4))
         self.comb += [
             self.data_in_csr[0].eq(self.output_value_ch0.storage), 
             self.data_in_csr[1].eq(self.output_value_ch1.storage),
-            self.cdc_fifo.sink.data.eq(Cat(self.data_in[0], self.data_in[1], self.data_in_csr[0], self.data_in_csr[1])),
-            self.cdc_fifo.sink.stb.eq(~ResetSignal("sys")),
-            Cat(self.data_in_cdc[0], self.data_in_cdc[1], self.data_in_csr_cdc[0], self.data_in_csr_cdc[1]).eq(self.cdc_fifo.source.data),
-            self.cdc_fifo.source.ack.eq(~ResetSignal("dco2d")),
         ]
 
         self.comb += [
-            Cat(manual_override, ch0_pd, ch1_pd).eq(self.dac_ctrl.storage),
+            Cat(manual_override, ch0_pd, ch1_pd, phase_shift_en, phase_shift_dir).eq(self.dac_ctrl.storage),
-            dac_pads.rst.eq(ResetSignal("dco2d")),
+            dac_pads.rst.eq(ResetSignal("sys")),
             dac_afe_pads.ch1_pd_n.eq(~ch0_pd),
             dac_afe_pads.ch2_pd_n.eq(~ch1_pd),
             output_data_ch0.eq(
-                Mux(manual_override, self.data_in_csr_cdc[0], self.data_in_cdc[0])
+                Mux(manual_override, self.data_in_csr[0], self.data_in[0])
             ),
             output_data_ch1.eq(
-                Mux(manual_override, self.data_in_csr_cdc[1], self.data_in_cdc[1])
+                Mux(manual_override, self.data_in_csr[1], self.data_in[1])
             ),
         ]
 
         self.specials += [
             Instance("ODDR", 
-                i_C=ClockSignal("dco2d"), 
+                i_C=ClockSignal("sys"), 
-                i_CE=~ResetSignal("dco2d"), 
+                i_CE=~ResetSignal("sys"), 
                 i_D1=output_data_ch0[lane], # DDR CLK Rising Edge
                 i_D2=output_data_ch1[lane], # DDR CLK Falling Edge
                 o_Q=dac_pads.data[lane],
                 p_DDR_CLK_EDGE="SAME_EDGE") 
             for lane in range(14)]
         self.specials += Instance("ODDR", 
-                i_C=ClockSignal("dco2d_45_degree"), 
+                i_C=ClockSignal("sys_45_degree"), 
-                i_CE=~ResetSignal("dco2d"), 
+                i_CE=~ResetSignal("sys"), 
                 i_D1=0, 
                 i_D2=1, 
                 o_Q=dac_pads.dclkio,

fast-servo/linien-gateware/fast_servo_platform.py

@@ -80,11 +80,13 @@ _io = [
         Subsignal("data0_n", Pins("E7 B6 E3 C1"), IOStandard("LVDS_25")),
         Subsignal("data1_p", Pins("A2 D5 F2 D7"), IOStandard("LVDS_25")),
         Subsignal("data1_n", Pins("A1 C4 F1 D6"), IOStandard("LVDS_25")),
-        Subsignal("dco_p", Pins("B4"), IOStandard("LVDS_25")),
-        Subsignal("dco_n", Pins("B3"), IOStandard("LVDS_25")),
         Subsignal("frame_p", Pins("B2"), IOStandard("LVDS_25")),
         Subsignal("frame_n", Pins("B1"), IOStandard("LVDS_25"))
     ),
+    ("adc_dco_clk", 0 ,
+        Subsignal("p", Pins("B4"), IOStandard("LVDS_25")),
+        Subsignal("n", Pins("B3"), IOStandard("LVDS_25")),
+    ),
 
     # ADC AFE
     ("adc_afe", 0,
@@ -194,7 +196,7 @@ _io = [
 
     # Si540 nRST
     ("nrst", 0, Pins("M7"), IOStandard("LVCMOS18")),
-
+    ("si5340_nlol", 0, Pins("P2"),IOStandard("LVCMOS18")),
 ]
 
 
@@ -271,7 +273,7 @@ ps7_config_board_preset = {
 
     # ETHERNET
     "PCW_ACT_ENET0_PERIPHERAL_FREQMHZ"  : "125",
-    "PCW_ENET0_PERIPHERAL_CLKSRC"       : "ARM PLL",
+    "PCW_ENET0_PERIPHERAL_CLKSRC"       : "IO PLL",
     "PCW_ENET0_PERIPHERAL_ENABLE"       : "1",
     "PCW_ENET0_ENET0_IO"                : "MIO 16 .. 27",
     "PCW_ENET0_GRP_MDIO_ENABLE"         : "1",
@@ -315,21 +317,23 @@ ps7_config_board_preset = {
 }
 
 class Platform(XilinxPlatform):
-    default_clk_name = "clk100"
+    default_clk_name = "adc_dco_clk_p"
-    default_clk_period = 10.0
+    default_clk_period = 4.0
 
     def __init__(self):
         XilinxPlatform.__init__(self, "xc7z015-clg485-1", _io, _connector_gpio + _connector_eem, toolchain="vivado")
         ps7_config = ps7_config_board_preset
         self.ps7_config = ps7_config
 
+        self.toolchain.with_phys_opt = True
+
         verilog_sources = os.listdir(verilog_dir)
         self.add_sources(verilog_dir, *verilog_sources)
 
     def do_finalize(self, fragment):
         try:
             XilinxPlatform.do_finalize(self, fragment)
-            self.add_period_constraint(self.lookup_request(self.default_clk_name, loose=True), self.default_clk_period)
+            self.add_period_constraint(self.lookup_request(self.default_clk_name), self.default_clk_period)
         except ValueError:
             pass
         except ConstraintError:

fast-servo/linien-gateware/fast_servo_soc.py

@@ -31,63 +31,91 @@ from fast_servo.gateware.cores.spi_phy import SpiInterface, SpiPhy
 
 
 class CRG(Module):
-    def __init__(self, platform):
+    def __init__(self, platform, dco_freq=250e6):
         self.ps_rst         = Signal()
         self.locked         = Signal()
+
+        dco_clk = platform.request("adc_dco_clk")
+        dco_clk_buf = Signal()
+        self.specials += Instance(
+            "IBUFGDS", i_I=dco_clk.p, i_IB=dco_clk.n, o_O=dco_clk_buf
+        )
+
         self.clock_domains.cd_sys         = ClockDomain()
+        self.clock_domains.cd_sys_45_degree = ClockDomain()
         self.clock_domains.cd_sys_double  = ClockDomain()
         self.clock_domains.cd_idelay      = ClockDomain()
 
-        # # #
-
-        # Clk.
-        clk100 = platform.request("clk100")
-        platform.add_period_constraint(clk100, 10.0)
-        self.clkin = clk100
-        clk100_buf = Signal()
-        self.specials += Instance("IBUFG", i_I=clk100, o_O=clk100_buf)
-
         clk_feedback = Signal()
         clk_feedback_buf = Signal()
 
         clk_sys = Signal()
+        clk_sys_45_degree = Signal()
+        clk_sys_double = Signal()
         clk_idelay = Signal()
 
+        self.ddr_clk_phase_shift_en = Signal()
+        self.ddr_clk_phase_incdec = Signal()
+        self.mmcm_ps_psdone = Signal()
+
+        si5340_nlol = platform.request("si5340_nlol")
+        si5340_nlol_buf = Signal()
+        self.specials += Instance("IBUF", i_I=si5340_nlol, o_O=si5340_nlol_buf)
+
+        platform.add_period_constraint(dco_clk.p, 1e9 / dco_freq)
         self.specials += [
             Instance(
-                "PLLE2_BASE",
+                "MMCME2_ADV",
                 p_BANDWIDTH="OPTIMIZED",
                 p_DIVCLK_DIVIDE=1,
                 p_CLKFBOUT_PHASE=0.0,
-                p_CLKFBOUT_MULT=10,
+                p_CLKFBOUT_MULT_F=4,  # VCO @ 1000 MHz
-                p_CLKIN1_PERIOD=10.0,
+                p_CLKIN1_PERIOD=(1e9 / dco_freq),
-                p_REF_JITTER1=0.01,
+                p_REF_JITTER1=0.06, # From LTC2195 Datasheet
                 p_STARTUP_WAIT="FALSE",
-                i_CLKIN1=clk100_buf,
+                i_CLKIN1=dco_clk_buf,
                 i_PWRDWN=0,
-                i_RST=self.ps_rst,
+                i_RST=self.ps_rst | ~si5340_nlol_buf,
                 i_CLKFBIN=clk_feedback_buf,
                 o_CLKFBOUT=clk_feedback,
-                p_CLKOUT0_DIVIDE=10,
+
-                p_CLKOUT0_PHASE=0.0,
+                p_CLKOUT0_USE_FINE_PS="True",
+                p_CLKOUT0_DIVIDE_F=8,
+                p_CLKOUT0_PHASE=45.0,
                 p_CLKOUT0_DUTY_CYCLE=0.5,
-                o_CLKOUT0=clk_sys,           # 100 MHz <- sys_clk
+                o_CLKOUT0=clk_sys_45_degree,  # 1000MHz / 8 -> 125MHz
-                p_CLKOUT1_DIVIDE=5,
+                o_LOCKED=self.locked,
+                
+                p_CLKOUT1_DIVIDE=8,
                 p_CLKOUT1_PHASE=0.0,
                 p_CLKOUT1_DUTY_CYCLE=0.5,
-                o_CLKOUT1=clk_idelay,       # 200 MHZ <- 2 * sys_clk = 2*100 MHz
+                o_CLKOUT1=clk_sys,  # 1000MHz / 8 -> 120MHz
-                o_LOCKED=self.locked,
+                
+                p_CLKOUT2_DIVIDE=4,
+                p_CLKOUT2_PHASE=0.0,
+                p_CLKOUT2_DUTY_CYCLE=0.5,
+                o_CLKOUT2=clk_sys_double,  # 1000MHz / 4 -> 250MHz
+
+                p_CLKOUT3_DIVIDE=5,
+                p_CLKOUT3_PHASE=0.0,
+                p_CLKOUT3_DUTY_CYCLE=0.5,
+                o_CLKOUT3=clk_idelay,  # 1000MHz / 5 -> 200MHz 
+
+                i_PSCLK=ClockSignal(),
+                i_PSEN=self.ddr_clk_phase_shift_en,
+                i_PSINCDEC=self.ddr_clk_phase_incdec,
+                o_PSDONE=self.mmcm_ps_psdone,
             )
         ]
 
         self.specials += Instance("BUFG", i_I=clk_feedback, o_O=clk_feedback_buf)
         self.specials += Instance("BUFG", i_I=clk_sys, o_O=self.cd_sys.clk)
+        self.specials += Instance("BUFG", i_I=clk_sys_45_degree, o_O=self.cd_sys_45_degree.clk)
+        self.specials += Instance("BUFG", i_I=clk_sys_double, o_O=self.cd_sys_double.clk)
         self.specials += Instance("BUFG", i_I=clk_idelay, o_O=self.cd_idelay.clk)
-        self.specials += Instance("BUFG", i_I=clk_idelay, o_O=self.cd_sys_double.clk)
+        
-
-
         # Ignore sys_clk to pll clkin path created by SoC's rst.
-        platform.add_false_path_constraints(self.cd_sys.clk, self.clkin)
+        platform.add_false_path_constraints(self.cd_sys.clk, dco_clk)
 
         self.specials += Instance("FD", p_INIT=1, i_D=~self.locked, i_C=self.cd_sys.clk, o_Q=self.cd_sys.rst)
 
@@ -117,6 +145,10 @@ class BaseSoC(PS7, AutoCSR):
 
         self.submodules.crg = CRG(platform)
 
+        # self.comb += self.afe_ctrl.storage[4].eq(self.crg.mmcm_rst)
+        # self.comb += self.afe_ctrl.storage[5].eq(self.crg.ddr_clk_phase_shift_en)
+        # self.comb += self.afe_ctrl.storage[6].eq(self.crg.ddr_clk_phase_incdec)
+
         # # # AXI to system bus bridge
         self.submodules.axi2sys = Axi2Sys()
         self.submodules.sys2csr = Sys2CSR()
@@ -147,10 +179,10 @@ class BaseSoC(PS7, AutoCSR):
         # self.add_main_adc(platform)
         self.submodules.adc = ADC(platform)
         self.csr_devices.append("adc")
-        platform.add_false_path_constraints(self.crg.cd_sys.clk, self.adc.crg.cd_dco2d.clk)
+        # platform.add_false_path_constraints(self.crg.cd_sys.clk, self.adc.crg.cd_dco2d.clk)
 
         # self.add_main_dac(platform)
-        self.submodules.dac = DAC(platform)
+        self.submodules.dac = DAC(platform, [self.crg.ddr_clk_phase_shift_en, self.crg.ddr_clk_phase_incdec,])
         self.csr_devices.append("dac")
         
         # DEBUG

fast-servo/linien-gui-add-afe_gain-combo-boxes.patch

@@ -0,0 +1,132 @@
+diff --git a/linien-gui/linien_gui/ui/general_panel.py b/linien-gui/linien_gui/ui/general_panel.py
+index cad2d91..499146d 100644
+--- a/linien-gui/linien_gui/ui/general_panel.py
++++ b/linien-gui/linien_gui/ui/general_panel.py
+@@ -48,6 +48,8 @@ class GeneralPanel(QtWidgets.QWidget):
+     polarityContainerFastOut2: QtWidgets.QWidget
+     polarityComboBoxFastOut2: QtWidgets.QComboBox
+     modulationChannelComboBox: QtWidgets.QComboBox
++    afeGainComboBoxFastIn1: QtWidgets.QComboBox
++    afeGainComboBoxFastIn2: QtWidgets.QComboBox
+ 
+     def __init__(self, *args, **kwargs) -> None:
+         super(GeneralPanel, self).__init__(*args, **kwargs)
+@@ -80,6 +82,14 @@ class GeneralPanel(QtWidgets.QWidget):
+             self.on_polarity_analog_out0_changed
+         )
+ 
++        self.afeGainComboBoxFastIn1.currentIndexChanged.connect(
++            self.on_afe_gain_in1_changed
++        )
++
++        self.afeGainComboBoxFastIn2.currentIndexChanged.connect(
++            self.on_afe_gain_in2_changed
++        )
++
+         for idx in range(1, 4):
+             element: CustomDoubleSpinBoxNoSign = getattr(
+                 self, f"analogOutComboBox{idx}"
+@@ -126,6 +136,9 @@ class GeneralPanel(QtWidgets.QWidget):
+         param2ui(self.parameters.polarity_fast_out2, self.polarityComboBoxFastOut2)
+         param2ui(self.parameters.polarity_analog_out0, self.polarityComboBoxAnalogOut0)
+ 
++        param2ui(self.parameters.adc_afe_10x_gain_1, self.afeGainComboBoxFastIn1)
++        param2ui(self.parameters.adc_afe_10x_gain_2, self.afeGainComboBoxFastIn2)
++
+         self.parameters.control_channel.add_callback(self.show_polarity_settings)
+         self.parameters.sweep_channel.add_callback(self.show_polarity_settings)
+         self.parameters.mod_channel.add_callback(self.show_polarity_settings)
+@@ -211,6 +224,14 @@ class GeneralPanel(QtWidgets.QWidget):
+         self.parameters.polarity_analog_out0.value = bool(polarity)
+         self.control.write_registers()
+ 
++    def on_afe_gain_in1_changed(self, polarity):
++        self.parameters.adc_afe_10x_gain_1.value = bool(polarity)
++        self.control.write_registers()
++
++    def on_afe_gain_in2_changed(self, polarity):
++        self.parameters.adc_afe_10x_gain_2.value = bool(polarity)
++        self.control.write_registers()    
++
+     def show_polarity_settings(self, *args):
+         used_channels = {
+             self.parameters.control_channel.value,
+diff --git a/linien-gui/linien_gui/ui/general_panel.ui b/linien-gui/linien_gui/ui/general_panel.ui
+index 6c2bd45..79f4580 100644
+--- a/linien-gui/linien_gui/ui/general_panel.ui
++++ b/linien-gui/linien_gui/ui/general_panel.ui
+@@ -508,6 +508,74 @@
+            </property>
+           </widget>
+          </item>
++         <item>
++          <layout class="QHBoxLayout" name="horizontalLayout_13">
++           <item>
++            <widget class="QLabel" name="label_22">
++             <property name="text">
++              <string>&lt;html&gt;&lt;head/&gt;&lt;body&gt;&lt;p&gt;&lt;span style=&quot; font-weight:600;&quot;&gt;FAST IN 1 GAIN&lt;/span&gt;&lt;/p&gt;&lt;/body&gt;&lt;/html&gt;</string>
++             </property>
++             <property name="textFormat">
++              <enum>Qt::AutoText</enum>
++             </property>
++            </widget>
++           </item>
++           <item>
++            <widget class="QComboBox" name="afeGainComboBoxFastIn1">
++             <property name="sizePolicy">
++              <sizepolicy hsizetype="Fixed" vsizetype="Fixed">
++               <horstretch>0</horstretch>
++               <verstretch>0</verstretch>
++              </sizepolicy>
++             </property>
++             <item>
++              <property name="text">
++               <string>1x</string>
++              </property>
++             </item>
++             <item>
++              <property name="text">
++               <string>10x</string>
++              </property>
++             </item>
++            </widget>
++           </item>
++          </layout>
++         </item>
++         <item>
++          <layout class="QHBoxLayout" name="horizontalLayout_14">
++           <item>
++            <widget class="QLabel" name="label_24">
++             <property name="text">
++              <string>&lt;html&gt;&lt;head/&gt;&lt;body&gt;&lt;p&gt;&lt;span style=&quot; font-weight:600;&quot;&gt;FAST IN 2 GAIN&lt;/span&gt;&lt;/p&gt;&lt;/body&gt;&lt;/html&gt;</string>
++             </property>
++             <property name="textFormat">
++              <enum>Qt::AutoText</enum>
++             </property>
++            </widget>
++           </item>
++           <item>
++            <widget class="QComboBox" name="afeGainComboBoxFastIn2">
++             <property name="sizePolicy">
++              <sizepolicy hsizetype="Fixed" vsizetype="Fixed">
++               <horstretch>0</horstretch>
++               <verstretch>0</verstretch>
++              </sizepolicy>
++             </property>
++             <item>
++              <property name="text">
++               <string>1x</string>
++              </property>
++             </item>
++             <item>
++              <property name="text">
++               <string>10x</string>
++              </property>
++             </item>
++            </widget>
++           </item>
++          </layout>
++         </item>
+          <item>
+           <widget class="QGroupBox" name="dualChannelMixingGroupBox">
+            <property name="title">

fast-servo/linien-gui-do-not-use-opengl.patch

@@ -0,0 +1,13 @@
+diff --git a/linien-gui/linien_gui/ui/plot_widget.py b/linien-gui/linien_gui/ui/plot_widget.py
+index f3b81ce..7d865a3 100644
+--- a/linien-gui/linien_gui/ui/plot_widget.py
++++ b/linien-gui/linien_gui/ui/plot_widget.py
+@@ -40,7 +40,7 @@ from pyqtgraph.Qt import QtCore
+ # NOTE: this is required for using a pen_width > 1. There is a bug though that causes
+ # the plot to be way too small. Therefore, we call PlotWidget.resize() after a while
+ pg.setConfigOptions(
+-    useOpenGL=True,
++    useOpenGL=False,
+     # by default, pyqtgraph tries to clean some things up using atexit. This causes
+     # problems with rpyc objects as their connection is already closed. Therefore, we
+     # disable this cleanup.

fast-servo/linien-gui-fast-servo-hardware-specific.patch

@@ -126,102 +126,3 @@ index 6d8af14..29c8a63 100644
            </property>
            <property name="singleStep">
             <double>0.100000000000000</double>
-@@ -105,82 +105,82 @@
-           </property>
-           <item>
-            <property name="text">
--            <string>3.8 kHz</string>
-+            <string>3.04 kHz</string>
-            </property>
-           </item>
-           <item>
-            <property name="text">
--            <string>1.9 kHz</string>
-+            <string>1.52 kHz</string>
-            </property>
-           </item>
-           <item>
-            <property name="text">
--            <string>954 Hz</string>
-+            <string>763 Hz</string>
-            </property>
-           </item>
-           <item>
-            <property name="text">
--            <string>477 Hz</string>
-+            <string>382 Hz</string>
-            </property>
-           </item>
-           <item>
-            <property name="text">
--            <string>238 Hz</string>
-+            <string>190 Hz</string>
-            </property>
-           </item>
-           <item>
-            <property name="text">
--            <string>119 Hz</string>
-+            <string>95 Hz</string>
-            </property>
-           </item>
-           <item>
-            <property name="text">
--            <string>59 Hz</string>
-+            <string>47 Hz</string>
-            </property>
-           </item>
-           <item>
-            <property name="text">
--            <string>30 Hz</string>
-+            <string>24 Hz</string>
-            </property>
-           </item>
-           <item>
-            <property name="text">
--            <string>15 Hz</string>
-+            <string>12 Hz</string>
-            </property>
-           </item>
-           <item>
-            <property name="text">
--            <string>7.5 Hz</string>
-+            <string>6 Hz</string>
-            </property>
-           </item>
-           <item>
-            <property name="text">
--            <string>3.7 Hz</string>
-+            <string>2.96 Hz</string>
-            </property>
-           </item>
-           <item>
-            <property name="text">
--            <string>1.9 Hz</string>
-+            <string>1.52 Hz</string>
-            </property>
-           </item>
-           <item>
-            <property name="text">
--            <string>0.93 Hz</string>
-+            <string>0.74 Hz</string>
-            </property>
-           </item>
-           <item>
-            <property name="text">
--            <string>0.47 Hz</string>
-+            <string>0.38 Hz</string>
-            </property>
-           </item>
-           <item>
-            <property name="text">
--            <string>0.23 Hz</string>
-+            <string>0.18 Hz</string>
-            </property>
-           </item>
-           <item>
-            <property name="text">
--            <string>0.12 Hz</string>
-+            <string>0.10 Hz</string>
-            </property>
-           </item>
-          </widget>

fast-servo/linien-module-iir-coeff-width-set-to-18bit.patch

@@ -0,0 +1,22 @@
+diff --git a/gateware/linien_module.py b/gateware/linien_module.py
+index a64714c..1d905de 100644
+--- a/gateware/linien_module.py
++++ b/gateware/linien_module.py
+@@ -47,7 +47,7 @@ from .lowlevel.scopegen import ScopeGen
+ 
+ 
+ class LinienLogic(Module, AutoCSR):
+-    def __init__(self, width=14, signal_width=25, chain_factor_width=8, coeff_width=25):
++    def __init__(self, width=14, signal_width=25, chain_factor_width=8, coeff_width=18):
+         self.init_csr(width, chain_factor_width)
+         self.init_submodules(width, signal_width)
+         self.connect_pid()
+@@ -154,7 +154,7 @@ class LinienModule(Module, AutoCSR):
+     def __init__(self, soc):
+         width = 14
+         signal_width = 25
+-        coeff_width = 25
++        coeff_width = 18
+         chain_factor_bits = 8
+ 
+         self.init_submodules(

fast-servo/linien-server-add-afe_ctrl-regs.patch

@@ -0,0 +1,34 @@
+diff --git a/linien-server/linien_server/parameters.py b/linien-server/linien_server/parameters.py
+index 287f304..fe482d7 100644
+--- a/linien-server/linien_server/parameters.py
++++ b/linien-server/linien_server/parameters.py
+@@ -154,6 +154,16 @@ class Parameters:
+         `error_signal_2_max`.
+         """
+ 
++        # ------------------- FAST SERVO PARAMETERS ---------------------------------------
++        self.adc_afe_10x_gain_1 = Parameter(start=0, min_=0, max_=1, restorable=True)
++        self.adc_afe_10x_gain_2 = Parameter(start=0, min_=0, max_=1, restorable=True)
++        """
++        Configures Fast INs AFE Gain:
++            0 -->  1x Gain
++            1 --> 10x Gain
++        """
++        
++
+         # ------------------- GENERAL PARAMETERS ---------------------------------------
+ 
+         self.mod_channel = Parameter(start=0, min_=0, max_=1, restorable=True)
+diff --git a/linien-server/linien_server/registers.py b/linien-server/linien_server/registers.py
+index 365c254..2b8f697 100644
+--- a/linien-server/linien_server/registers.py
++++ b/linien-server/linien_server/registers.py
+@@ -173,6 +173,8 @@ class Registers:
+             gpio_n_do0_en=csrmap.signals.index("zero"),
+             gpio_n_do1_en=csrmap.signals.index("zero"),
+             logic_slow_decimation=16,
++            # Fast Servo Paramters
++            adc_afe_ctrl=(self.parameters.adc_afe_10x_gain_2.value << 1 | self.parameters.adc_afe_10x_gain_1.value)
+         )
+ 
+         for instruction_idx, [wait_for, peak_height] in enumerate(

fast-servo/linien-server-cli.patch

@@ -0,0 +1,73 @@
+diff --git a/linien-client/linien_client/deploy.py b/linien-client/linien_client/deploy.py
+index 7355cc3..876f1ec 100644
+--- a/linien-client/linien_client/deploy.py
++++ b/linien-client/linien_client/deploy.py
+@@ -83,14 +83,14 @@ def start_remote_server(
+         if (local_version != remote_version) and not ("dev" in local_version):
+             raise InvalidServerVersionException(local_version, remote_version)
+ 
+-        logger.debug("Sending credentials")
+-        conn.run(
+-            'python3 -c "from linien_common.communication import write_hash_to_file;'
+-            f"write_hash_to_file('{hash_username_and_password(device.username, device.password)}')\"",  # noqa E501
+-            out_stream=out_stream,
+-            err_stream=out_stream,
+-            warn=True,
+-        )
++        # logger.debug("Sending credentials")
++        # conn.run(
++        #     'python3 -c "from linien_common.communication import write_hash_to_file;'
++        #     f"write_hash_to_file('{hash_username_and_password(device.username, device.password)}')\"",  # noqa E501
++        #     out_stream=out_stream,
++        #     err_stream=out_stream,
++        #     warn=True,
++        # )
+ 
+         logger.debug("Starting server")
+         conn.run(
+diff --git a/linien-server/linien_server/cli.py b/linien-server/linien_server/cli.py
+index 7781c74..827d04f 100644
+--- a/linien-server/linien_server/cli.py
++++ b/linien-server/linien_server/cli.py
+@@ -44,20 +44,19 @@ class LinienServerCLI:
+ 
+     def start(self) -> None:
+         """Start the Linien server as a systemd service."""
+-        copy_systemd_service_file()
+         logger.info("Starting Linien server")
+-        subprocess.run(["systemctl", "start", "linien-server.service"])
++        subprocess.run(["sv", "up", "/etc/service/linien-server"])
+         logger.info("Started Linien server")
+ 
+     def stop(self) -> None:
+         """Stop the Linien server running as a systemd service."""
+         logger.info("Stopping Linien server")
+-        subprocess.run(["systemctl", "stop", "linien-server.service"])
++        subprocess.run(["sv", "down", "/etc/service/linien-server"])
+         logger.info("Stopped Linien server")
+ 
+     def status(self) -> None:
+         """Check the status of the Linien server."""
+-        subprocess.run(["journalctl", "-u", "linien-server.service"])
++        subprocess.run(["sv", "status", "/etc/service/linien-server"])
+ 
+     def run(self, fake: bool = False, host: Optional[str] = None) -> None:
+         """
+@@ -89,15 +88,14 @@ class LinienServerCLI:
+ 
+     def enable(self) -> None:
+         """Enable the Linien server to start on boot."""
+-        copy_systemd_service_file()
+         logger.info("Enabling Linien server")
+-        subprocess.run(["systemctl", "enable", "linien-server.service"])
++        subprocess.run(["rm", "/etc/service/linien-server/down"])
+         logger.info("Enabled Linien server")
+ 
+     def disable(self) -> None:
+         """Disable the Linien server from starting on boot."""
+         logger.info("Disabling Linien server")
+-        subprocess.run(["systemctl", "disable", "linien-server.service"])
++        subprocess.run(["touch", "/etc/service/linien-server/down"])
+         logger.info("Disabled Linien server")
+ 
+ 

fast-servo/linien_module_pipeline.patch

@@ -1,13 +1,12 @@
 diff --git a/gateware/linien_module.py b/gateware/linien_module.py
-index a958896..a64714c 100644
+index 54b6285..c3f8d14 100644
 --- a/gateware/linien_module.py
 +++ b/gateware/linien_module.py
-@@ -233,23 +233,46 @@ class LinienModule(Module, AutoCSR):
+@@ -233,30 +233,52 @@ class LinienModule(Module, AutoCSR):
              self.fast_a.adc.eq(soc.analog.adc_a),
              self.fast_b.adc.eq(soc.analog.adc_b),
          ]
 -
-+        
          # now, we combine the output of the two paths, with a variable factor each.
          mixed = Signal(
              (2 + ((signal_width + 1) + self.logic.chain_a_factor.size), True)
@@ -42,16 +41,26 @@ index a958896..a64714c 100644
 -                    (self.logic.chain_a_factor.storage * self.fast_a.out_i)
 -                    + (self.logic.chain_b_factor.storage * self.fast_b.out_i)
 -                    + (self.logic.combined_offset_signed << (chain_factor_bits + s))
-+                    chain_a_factor_mult_fast_a_out_i
++                    (chain_a_factor_mult_fast_a_out_i
 +                    + chain_b_factor_mult_fast_b_out_i
-+                    + combined_offset_signed_left_shifted
++                    + combined_offset_signed_left_shifted) >> chain_factor_bits
                  ),
              ).Else(
                  mixed.eq(
 -                    (self.fast_a.out_i << chain_factor_bits)
 -                    + (self.logic.combined_offset_signed << (chain_factor_bits + s))
-+                    fast_a_out_i_left_shifted
+-                )
-+                    + combined_offset_signed_left_shifted
++                    (fast_a_out_i_left_shifted
-                 )
++                    + combined_offset_signed_left_shifted) >> chain_factor_bits
++                ),
              )
          ]
+ 
+         mixed_limited = Signal((signal_width, True))
+-        self.comb += [
+-            self.logic.limit_error_signal.x.eq(mixed >> chain_factor_bits),
++        self.sync += [
++            self.logic.limit_error_signal.x.eq(mixed),
+             mixed_limited.eq(self.logic.limit_error_signal.y),
+         ]
+ 

fast-servo/pyfastservo/adc.py

@@ -85,26 +85,6 @@ def perform_bitslip():
             print(f"No bitslip required; Current frame: 0x{current_frame:02x}")
             return
 
-def mmcm_rst():
-    curr_cfg = read_from_memory(ADC_AFE_CTRL_ADDR, 1)[0] & 0x0F
-    write_to_memory(ADC_AFE_CTRL_ADDR, 0x10 | curr_cfg) # Reset MMCM
-    write_to_memory(ADC_AFE_CTRL_ADDR, 0x00 | curr_cfg) # Release MMCM Reset
-    while not(read_frame() & 0x10):
-        print(f"Waiting for MMCM to lock")
-        time.sleep(0.001)
-
-def inc_ddr_clk_phase():
-    curr_cfg = read_from_memory(ADC_AFE_CTRL_ADDR, 1)[0] & 0x1F
-    write_to_memory(ADC_AFE_CTRL_ADDR, 0x40 | curr_cfg) # Set MMCM Phase Shift to be INC
-    write_to_memory(ADC_AFE_CTRL_ADDR, 0x60 | curr_cfg) # Assert MMCM Phase Shift EN High
-    write_to_memory(ADC_AFE_CTRL_ADDR, curr_cfg)        # Deassert MMCM Phase Shift EN High
-
-def dec_ddr_clk_phase():
-    curr_cfg = read_from_memory(ADC_AFE_CTRL_ADDR, 1)[0] & 0x1F
-    write_to_memory(ADC_AFE_CTRL_ADDR, 0x00 | curr_cfg) # Set MMCM Phase Shift to be DEC
-    write_to_memory(ADC_AFE_CTRL_ADDR, 0x20 | curr_cfg) # Assert MMCM Phase Shift EN High
-    write_to_memory(ADC_AFE_CTRL_ADDR, curr_cfg)        # Deassert MMCM Phase Shift EN High
-
 def find_edge():
     prev_frame = read_frame()
     for tap_delay in range(32):
@@ -190,9 +170,6 @@ def configure_ltc2195():
             0x03: (test_pattern & 0xFF00) >> 8,
             0x04: test_pattern & 0xFF
         })
-
-        # ADC software reset put its PLL to sleep momentarily. Thus, MMCM needs to be reset as well.
-        mmcm_rst()
         
         # Performing Word Align
         perform_bitslip()

fast-servo/pyfastservo/dac.py

@@ -37,6 +37,17 @@ MAIN_DAC_BUS = 2
 MAIN_DAC_DEVICE = 0
 DAC_VERSION = 0x0A
 
+def inc_ddr_clk_phase():
+    curr_cfg = read_from_memory(CTRL_ADDR, 1)[0] & 0x07
+    write_to_memory(CTRL_ADDR, 0x10 | curr_cfg) # Set MMCM Phase Shift to be INC
+    write_to_memory(CTRL_ADDR, 0x18 | curr_cfg) # Assert MMCM Phase Shift EN High
+    write_to_memory(CTRL_ADDR, curr_cfg)        # Deassert MMCM Phase Shift EN High
+
+def dec_ddr_clk_phase():
+    curr_cfg = read_from_memory(CTRL_ADDR, 1)[0] & 0x07
+    write_to_memory(CTRL_ADDR, 0x00 | curr_cfg) # Set MMCM Phase Shift to be DEC
+    write_to_memory(CTRL_ADDR, 0x08 | curr_cfg) # Assert MMCM Phase Shift EN High
+    write_to_memory(CTRL_ADDR, curr_cfg)        # Deassert MMCM Phase Shift EN High
 
 def spi_write(spi, address, value):
     spi.xfer2([address, value])

fast-servo/pyfastservo/si5340.py

@@ -143,8 +143,8 @@ def configure_si5340():
             (0x0235, 0x00),  # M_NUM
             (0x0236, 0x00),
             (0x0237, 0x00),
-            (0x0238, 0x80),
+            (0x0238, 0xA0),
-            (0x0239, 0x89),
+            (0x0239, 0x8C),
             (0x023A, 0x00),
             (0x023B, 0x00),  # M_DEN
             (0x023C, 0x00),
@@ -156,13 +156,13 @@ def configure_si5340():
             (0x0303, 0x00),
             (0x0304, 0x00),
             (0x0305, 0x00),
-            (0x0306, 0x21),
+            (0x0306, 0x1B),
             (0x0307, 0x00),
             (0x0308, 0x00),  # N0_DEN
             (0x0309, 0x00),
             (0x030A, 0x00),
             (0x030B, 0x80),
-            (0x030C, 0x01), # N0_UPDATE
+            (0x030C, 0x01),  # N0_UPDATE
 
             # N1 Configuration (1:1 ratio)
             (0x030D, 0x00),  # N1_NUM
@@ -170,11 +170,11 @@ def configure_si5340():
             (0x030F, 0x00),
             (0x0310, 0x00),
             (0x0311, 0x00),
-            (0x0312, 0x01),
+            (0x0312, 0x00),
             (0x0313, 0x00),  # N1_DEN
             (0x0314, 0x00),
             (0x0315, 0x00),
-            (0x0316, 0x01),
+            (0x0316, 0x00),
             (0x0317, 0x01),  # N1_UPDATE
 
             # N2 Configuration (1:1 ratio)
@@ -183,11 +183,11 @@ def configure_si5340():
             (0x031A, 0x00),
             (0x031B, 0x00),
             (0x031C, 0x00),
-            (0x031D, 0x01),
+            (0x031D, 0x00),
             (0x031E, 0x00),  # N2_DEN
             (0x031F, 0x00),
             (0x0320, 0x00),
-            (0x0321, 0x01),
+            (0x0321, 0x00),
             (0x0322, 0x01),  # N2_UPDATE
 
             # N3 Configuration (1:1 ratio)
@@ -196,11 +196,11 @@ def configure_si5340():
             (0x0325, 0x00),
             (0x0326, 0x00),
             (0x0327, 0x00),
-            (0x0328, 0x01),
+            (0x0328, 0x00),
             (0x0329, 0x00),  # N3_DEN
             (0x032A, 0x00),
             (0x032B, 0x00),
-            (0x032C, 0x01),
+            (0x032C, 0x00),
             (0x032D, 0x01),  # N3_UPDATE
 
             # Output configuration

flake.lock

@@ -18,11 +18,11 @@
     },
     "nixpkgs": {
       "locked": {
-        "lastModified": 1734323986,
+        "lastModified": 1736867362,
-        "narHash": "sha256-m/lh6hYMIWDYHCAsn81CDAiXoT3gmxXI9J987W5tZrE=",
+        "narHash": "sha256-i/UJ5I7HoqmFMwZEH6vAvBxOrjjOJNU739lnZnhUln8=",
         "owner": "NixOS",
         "repo": "nixpkgs",
-        "rev": "394571358ce82dff7411395829aa6a3aad45b907",
+        "rev": "9c6b49aeac36e2ed73a8c472f1546f6d9cf1addc",
         "type": "github"
       },
       "original": {
@@ -40,11 +40,11 @@
         ]
       },
       "locked": {
-        "lastModified": 1699416673,
+        "lastModified": 1736697818,
-        "narHash": "sha256-uJ6QnU7hFUYZsz6J/HIBEpLW0bS7GLQOo6ccKtoZ68k=",
+        "narHash": "sha256-JqqQO9W2s64vt6q2XrAY1ml0l7ff+7HbY5xCUhJJFmM=",
         "owner": "cleverca22",
         "repo": "not-os",
-        "rev": "79ff6e6fe0b64bf8b8d38363b2bb0dea0cd5a686",
+        "rev": "c556294ad82fb256082ca0a787cc5da7cb4e91e3",
         "type": "github"
       },
       "original": {
@@ -64,11 +64,11 @@
     "src-migen": {
       "flake": false,
       "locked": {
-        "lastModified": 1727677091,
+        "lastModified": 1735131698,
-        "narHash": "sha256-Zg3SQnTwMM/VkOGKogbPyuCC2NhLy8HB2SPEUWWNgCU=",
+        "narHash": "sha256-P4vaF+9iVekRAC2/mc9G7IwI6baBpPAxiDQ8uye4sAs=",
         "owner": "m-labs",
         "repo": "migen",
-        "rev": "c19ae9f8ae162ffe2d310a92bfce53ac2a821bc8",
+        "rev": "4c2ae8dfeea37f235b52acb8166f12acaaae4f7c",
         "type": "github"
       },
       "original": {
@@ -80,11 +80,11 @@
     "src-misoc": {
       "flake": false,
       "locked": {
-        "lastModified": 1729234629,
+        "lastModified": 1736416570,
-        "narHash": "sha256-TLsTCXV5AC2xh+bS7EhBVBKqdqIU3eKrnlWcFF9LtAM=",
+        "narHash": "sha256-tbcN/fzejZIaYbTbwk8Ir1glYevESqMinMeDB3z8oxg=",
         "ref": "refs/heads/master",
-        "rev": "6085a312bca26adeca6584e37d08c8ba2e1d6e38",
+        "rev": "1f5318e9edc1085ac77e9b85b8f5e03371dba54c",
-        "revCount": 2460,
+        "revCount": 2464,
         "submodules": true,
         "type": "git",
         "url": "https://github.com/m-labs/misoc.git"

flake.nix

@@ -31,14 +31,20 @@
             ./fast-servo/linien-common-fast-servo-hardware-specific.patch
             ./fast-servo/linien-server-fast-servo-hardware-specific.patch
             ./fast-servo/linien-gui-fast-servo-hardware-specific.patch
+            ./fast-servo/linien-gui-add-afe_gain-combo-boxes.patch
+            ./fast-servo/linien-gui-do-not-use-opengl.patch
             ./fast-servo/linien-client-ssh-port-change.patch
             ./fast-servo/linien-server-fast-servo.patch
+            ./fast-servo/linien-server-cli.patch
+            ./fast-servo/linien-server-add-afe_ctrl-regs.patch
             ./fast-servo/linien-gateware-fast-servo.patch 
-            ./fast-servo/autolock_pipeline.patch
+            ./fast-servo/linien-gateware-autolock-pipeline.patch
-            ./fast-servo/iir_pipeline.patch
+            ./fast-servo/linien-module-iir-coeff-width-set-to-18bit.patch
             ./fast-servo/linien_module_pipeline.patch
             ./fast-servo/pid_pipeline.patch
             ./fast-servo/pid_err_sig_pipeline.patch
+            ./fast-servo/linien-gateware-chain-pipeline.patch
+            ./fast-servo/linien-demodulate_add_pipeline.patch
           ];
       };
 
@@ -52,6 +58,7 @@
           ./not-os-patches/pr-30.patch
           ./not-os-patches/pr-31.patch
           ./not-os-patches/pr-33.patch
+          ./not-os-patches/pr-34.patch
           ./not-os-patches/iproute2.patch
         ];
       };
@@ -348,6 +355,7 @@
         installPhase = ''
           mkdir -p $out $out/nix-support
           cp gateware/build/top.bit $out
+          cp gateware/build $out -r
           cp linien-server/linien_server/gateware.bin $out
           cp linien-server/linien_server/csrmap.py $out
           echo file binary-dist $out/top.bit >> $out/nix-support/hydra-build-products
@@ -420,9 +428,17 @@
                 cp ${fast-servo-gateware}/gateware.bin /lib/firmware/
                 echo gateware.bin > /sys/class/fpga_manager/fpga0/firmware
 
-                # Run device init scripts
+                # Reset the PL and initialize PL, ADC and DAC clock
-                echo "Initializing clock generator, ADC, and DAC..."
+                echo "Configuring Si5340 to generate Clocks"
-                python3 -m pyfastservo.initialize
+                python3 -m pyfastservo.si5340
+
+                # Iniailize ADC
+                echo "Initialize ADC"
+                python3 -m pyfastservo.adc
+
+                # Initialize DAC
+                echo "Initialize DAC"
+                python3 -m pyfastservo.dac
               '';
             })];
           system = "x86_64-linux";
@@ -641,6 +657,9 @@
     in rec {
       devShell.x86_64-linux = pkgs.mkShell {
         name = "nix-servo-dev_shell";
+        packages = [
+          vivado
+        ];
         buildInputs = with pkgs.python3Packages; [ 
           matplotlib
         ] ++ [ linien-common linien-client linien-gui ];

not-os-patches/pr-29.patch

@@ -26,16 +26,3 @@ index 7eaee32..c1881cb 100644
  
      # nix-build -A system.build.toplevel && du -h $(nix-store -qR result) --max=0 -BM|sort -n
      system.build.toplevel = pkgs.runCommand "not-os" {
-diff --git a/systemd-compat.nix b/systemd-compat.nix
-index 11464c6..cb223b8 100644
---- a/systemd-compat.nix
-+++ b/systemd-compat.nix
-@@ -9,6 +9,8 @@ with lib;
-     };
-     systemd.user = mkOption {
-     };
-+    systemd.tmpfiles = mkOption {
-+    };
-   };
-   config = {
-   };

not-os-patches/pr-34.patch

@@ -0,0 +1,20 @@
+diff --git a/zynq_image.nix b/zynq_image.nix
+index 069fe89..979b760 100644
+--- a/zynq_image.nix
++++ b/zynq_image.nix
+@@ -51,6 +51,15 @@ in {
+         hostname ${config.networking.hostName}
+         exec setsid agetty ttyPS0 115200
+       '';
++      "service/linien-server/run".source = pkgs.writeShellScript "linien-server" ''
++        exec 2>&1
++        exec setsid linien-server run
++      '';
++      "service/linien-server/log/run".source = pkgs.writeShellScript "linien-server-logger" ''
++        exec 2>&1
++        mkdir -p /root/linien-server-log
++        exec svlogd -tt /root/linien-server-log
++      '';
+       "pam.d/other".text = ''
+         auth     sufficient pam_permit.so
+         account  required pam_permit.so