pyfastservo: add note for dac output override

- Changing depth to 4 has resolved cdc issue

fast-servo/fast-servo.dts

@@ -1,7 +1,7 @@
-# 0 "my_dts/system-top.dts"
+# 0 "system-top.dts"
 # 0 "<built-in>"
 # 0 "<command-line>"
-# 1 "my_dts/system-top.dts"
+# 1 "system-top.dts"
 
 
 
@@ -10,8 +10,8 @@
 
 
 /dts-v1/;
-# 1 "my_dts/zynq-7000.dtsi" 1
+# 1 "zynq-7000.dtsi" 1
-# 15 "my_dts/zynq-7000.dtsi"
+# 15 "zynq-7000.dtsi"
 / {
  #address-cells = <1>;
  #size-cells = <1>;
@@ -564,8 +564,8 @@
   };
  };
 };
-# 10 "my_dts/system-top.dts" 2
+# 10 "system-top.dts" 2
-# 1 "my_dts/pcw.dtsi" 1
+# 1 "pcw.dtsi" 1
 
 
 
@@ -641,7 +641,48 @@
  fclk-enable = <0x0>;
  ps-clk-frequency = <33333333>;
 };
-# 11 "my_dts/system-top.dts" 2
+# 11 "system-top.dts" 2
+# 1 "system-user.dtsi" 1
+
+
+&spi0 {
+    is-decoded-cs = <1>;
+    num-cs = <4>;
+
+    spidev@1 {
+        compatible = "rohm,dh2228fv";
+        spi-max-frequency = <50000000>;
+        reg = <1>;
+    };
+
+    spidev@2 {
+        compatible = "rohm,dh2228fv";
+        spi-max-frequency = <50000000>;
+        reg = <2>;
+    };
+
+    spidev@3 {
+        compatible = "rohm,dh2228fv";
+        spi-max-frequency = <50000000>;
+        reg = <3>;
+    };
+
+    spidev@4 {
+        compatible = "rohm,dh2228fv";
+        spi-max-frequency = <50000000>;
+        reg = <4>;
+    };
+};
+
+&spi1 {
+
+    spidev@0 {
+        compatible = "rohm,dh2228fv";
+        spi-max-frequency = <50000000>;
+        reg = <0>;
+    };
+};
+# 12 "system-top.dts" 2
 / {
  model = "Sinara Fast Servo board";
  chosen {

fast-servo/linien-gateware/README.md

@@ -1,5 +1,5 @@
 ## Source Repository
-Files in this directory were copied from [elhep/Fast-Servo-Frimware](https://github.com/elhep/Fast-Servo-Firmware/tree/master/fast_servo/gateware).
+Files in this directory were copied from [elhep/Fast-Servo-Firmware](https://github.com/elhep/Fast-Servo-Firmware/tree/master/fast_servo/gateware).
 
 ## Commit ID
 The files were copied from commit ID [7fae40c](https://github.com/elhep/Fast-Servo-Firmware/commit/7fae40c0f872a91218be378f8289b98b1e366729).

fast-servo/linien-gateware/cores/adc.py

@@ -20,13 +20,15 @@
 from migen import *
 from migen.genlib.cdc import MultiReg
 from misoc.interconnect.csr import AutoCSR, CSRStatus, CSRStorage
+from misoc.interconnect.stream import AsyncFIFO
 
 
-class _CRG(Module):
+class CRG(Module):
     def __init__(self, platform, dco_clk, dco_freq=200e6):
         self.clock_domains.cd_dco = ClockDomain()
         self.clock_domains.cd_dco2x = ClockDomain()
         self.clock_domains.cd_dco2d = ClockDomain()
+        self.clock_domains.cd_dco2d_45_degree = ClockDomain()
         dco_clk_p, dco_clk_n = dco_clk
 
         dco_clk_buf = Signal()
@@ -41,59 +43,83 @@ class _CRG(Module):
         clk_dco = Signal()
         clk_dco2x = Signal()
         clk_dco2d = Signal()
+        clk_dco2d_45_degree = Signal()
+        mmcm_ps_psdone = Signal()
+
         self.locked = Signal()
+        self.mmcm_rst = Signal()
+        self.ddr_clk_phase_shift_en = Signal()
+        self.ddr_clk_phase_incdec = Signal()
 
         platform.add_period_constraint(dco_clk_p, 1e9 / dco_freq)
         self.specials += [
             Instance(
-                "PLLE2_BASE",
+                "MMCME2_ADV",
                 p_BANDWIDTH="OPTIMIZED",
                 p_DIVCLK_DIVIDE=1,
                 p_CLKFBOUT_PHASE=0.0,
-                p_CLKFBOUT_MULT=4,  # VCO @ 800 MHz
+                p_CLKFBOUT_MULT_F=4,  # VCO @ 800 MHz
                 p_CLKIN1_PERIOD=(1e9 / dco_freq),
                 p_REF_JITTER1=0.01,
                 p_STARTUP_WAIT="FALSE",
                 i_CLKIN1=dco_clk_buf,
                 i_PWRDWN=0,
-                i_RST=ResetSignal("sys"),
+                i_RST=ResetSignal("sys") | self.mmcm_rst,
                 i_CLKFBIN=clk_feedback_buf,
                 o_CLKFBOUT=clk_feedback,
-                p_CLKOUT0_DIVIDE=4,
+
-                p_CLKOUT0_PHASE=0.0,
+                p_CLKOUT0_USE_FINE_PS="TRUE",
+                p_CLKOUT0_DIVIDE_F=8,
+                p_CLKOUT0_PHASE=45.0,
                 p_CLKOUT0_DUTY_CYCLE=0.5,
-                o_CLKOUT0=clk_dco,  # 200 MHz <- dco_clk
+                o_CLKOUT0=clk_dco2d_45_degree,  # 100 MHz <- dco_clk / 2 = 200 MHz / 2
+                o_LOCKED=self.locked,
+
                 p_CLKOUT1_DIVIDE=2,
                 p_CLKOUT1_PHASE=0.0,
                 p_CLKOUT1_DUTY_CYCLE=0.5,
                 o_CLKOUT1=clk_dco2x,  # 400 MHZ <- 2 * dco_clk = 2*200 MHz
+                
                 p_CLKOUT2_DIVIDE=8,
                 p_CLKOUT2_PHASE=0.0,
                 p_CLKOUT2_DUTY_CYCLE=0.5,
                 o_CLKOUT2=clk_dco2d,  # 100 MHz <- dco_clk / 2 = 200 MHz / 2
-                o_LOCKED=self.locked,
+                
+                p_CLKOUT3_DIVIDE=4,
+                p_CLKOUT3_PHASE=0.0,
+                p_CLKOUT3_DUTY_CYCLE=0.5,
+                o_CLKOUT3=clk_dco,  # 200 MHz <- dco_clk
+
+                i_PSCLK=ClockSignal(),
+                i_PSEN=self.ddr_clk_phase_shift_en,
+                i_PSINCDEC=self.ddr_clk_phase_incdec,
+                o_PSDONE=mmcm_ps_psdone,
             )
         ]
 
         self.specials += Instance("BUFG", i_I=clk_feedback, o_O=clk_feedback_buf)
         self.specials += Instance("BUFG", i_I=clk_dco, o_O=self.cd_dco.clk)
         self.specials += Instance("BUFG", i_I=clk_dco2d, o_O=self.cd_dco2d.clk)
+        self.specials += Instance("BUFG", i_I=clk_dco2d_45_degree, o_O=self.cd_dco2d_45_degree.clk)
         self.specials += Instance("BUFG", i_I=clk_dco2x, o_O=self.cd_dco2x.clk)
 
+        # Ignore dco2d to mmcm dco_clk path created by SoC's rst.
+        platform.add_false_path_constraints(self.cd_dco2d.clk, dco_clk_buf)
+        self.specials += Instance("FD", p_INIT=1, i_D=~self.locked, i_C=self.cd_dco2d.clk, o_Q=self.cd_dco2d.rst)
 
 class ADC(Module, AutoCSR):
     def __init__(self, platform, dco_freq=200e6):
         adc_pads = platform.request("adc")
         afe_pads = platform.request("adc_afe")
 
-        self.frame_csr = CSRStatus(4)
+        self.frame_csr = CSRStatus(5)
         self.data_ch0 = CSRStatus(16)
         self.data_ch1 = CSRStatus(16)
 
         self.tap_delay = CSRStorage(5)
         self.bitslip_csr = CSRStorage(1)
 
-        self.afe_ctrl = CSRStorage(4)
+        self.afe_ctrl = CSRStorage(7)
 
         tap_delay_val = Signal(5)
         bitslip = Signal()
@@ -105,7 +131,17 @@ class ADC(Module, AutoCSR):
         ch2_shdn = Signal()
 
         self.data_out = [Signal(16, reset_less=True), Signal(16, reset_less=True)]
+        self.data_out_cdc = [Signal(16, reset_less=True), Signal(16, reset_less=True)]
         self.s_frame = Signal(4)
+        self.s_frame_cdc = Signal(4)
+
+        self.submodules.cdc_fifo = ClockDomainsRenamer({"write": "dco2d", "read": "sys"})(AsyncFIFO([("data", 36)], 4))
+        self.comb += [
+            self.cdc_fifo.sink.data.eq(Cat(self.data_out_cdc[0], self.data_out_cdc[1], self.s_frame_cdc)),
+            self.cdc_fifo.sink.stb.eq(~ResetSignal("dco2d")),
+            Cat(self.data_out[0], self.data_out[1], self.s_frame).eq(self.cdc_fifo.source.data),
+            self.cdc_fifo.source.ack.eq(~ResetSignal("sys")),
+        ]
 
         ###
 
@@ -117,11 +153,14 @@ class ADC(Module, AutoCSR):
             # dco_clk.n.eq(adc_pads.dco_n),
             tap_delay_val.eq(self.tap_delay.storage),
             Cat(ch1_gain_x10, ch2_gain_x10, ch1_shdn, ch2_shdn).eq(
-                self.afe_ctrl.storage
+                self.afe_ctrl.storage[0:4]
             ),
         ]
 
-        self.submodules._crg = _CRG(platform, dco_clk, dco_freq)
+        self.submodules.crg = CRG(platform, dco_clk, dco_freq)
+        self.comb += self.afe_ctrl.storage[4].eq(self.crg.mmcm_rst)
+        self.comb += self.afe_ctrl.storage[5].eq(self.crg.ddr_clk_phase_shift_en)
+        self.comb += self.afe_ctrl.storage[6].eq(self.crg.ddr_clk_phase_incdec)
 
         self.specials += MultiReg(self.bitslip_csr.re, bitslip_re_dco_2d, "dco2d")
         self.sync.dco2d += [
@@ -129,7 +168,8 @@ class ADC(Module, AutoCSR):
         ]
 
         self.comb += [
-            self.frame_csr.status.eq(self.s_frame),
+            self.frame_csr.status[0:4].eq(self.s_frame[0:4]),
+            self.frame_csr.status[4].eq(self.crg.locked),
             self.data_ch0.status.eq(self.data_out[0]),
             self.data_ch1.status.eq(self.data_out[1]),
         ]
@@ -146,7 +186,7 @@ class ADC(Module, AutoCSR):
 
         self.specials += Instance(
             "LTC2195",
-            i_rst_in=ResetSignal("sys"),
+            i_rst_in=ResetSignal("dco2d"),
             i_clk200=ClockSignal("idelay"),
             i_DCO=ClockSignal("dco"),
             i_DCO_2D=ClockSignal("dco2d"),
@@ -158,9 +198,9 @@ class ADC(Module, AutoCSR):
             i_D1_in_n=adc_pads.data1_n,
             i_bitslip=bitslip,
             i_delay_val=tap_delay_val,
-            o_ADC0_out=self.data_out[1],        # LANES swapped on hardware
+            o_ADC0_out=self.data_out_cdc[1],        # LANES swapped on hardware
-            o_ADC1_out=self.data_out[0],
+            o_ADC1_out=self.data_out_cdc[0],
-            o_FR_out=self.s_frame,
+            o_FR_out=self.s_frame_cdc,
             o_o_data_from_pins=dummy,
             o_idelay_rdy=dummy_idelay_rdy,
         )

fast-servo/linien-gateware/cores/dac.py

@@ -20,6 +20,7 @@
 from migen import *
 from misoc.interconnect.csr import AutoCSR, CSRStorage
 from migen.genlib.io import DDROutput
+from misoc.interconnect.stream import AsyncFIFO
 
 
 class DAC(Module, AutoCSR):
@@ -38,37 +39,51 @@ class DAC(Module, AutoCSR):
         output_data_ch1 = Signal(14)
 
         self.data_in = [Signal(14, reset_less=True), Signal(14, reset_less=True)]
+        self.data_in_csr = [Signal(14, reset_less=True), Signal(14, reset_less=True)]
+        
+        self.data_in_cdc = [Signal(14, reset_less=True), Signal(14, reset_less=True)]
+        self.data_in_csr_cdc = [Signal(14, reset_less=True), Signal(14, reset_less=True)]
         platform.add_period_constraint(dac_pads.dclkio, 10.0)
 
+        self.submodules.cdc_fifo = ClockDomainsRenamer({"write": "sys", "read": "dco2d"})(AsyncFIFO([("data", 56)], 4))
+        self.comb += [
+            self.data_in_csr[0].eq(self.output_value_ch0.storage), 
+            self.data_in_csr[1].eq(self.output_value_ch1.storage),
+            self.cdc_fifo.sink.data.eq(Cat(self.data_in[0], self.data_in[1], self.data_in_csr[0], self.data_in_csr[1])),
+            self.cdc_fifo.sink.stb.eq(~ResetSignal("sys")),
+            Cat(self.data_in_cdc[0], self.data_in_cdc[1], self.data_in_csr_cdc[0], self.data_in_csr_cdc[1]).eq(self.cdc_fifo.source.data),
+            self.cdc_fifo.source.ack.eq(~ResetSignal("dco2d")),
+        ]
+
         self.comb += [
             Cat(manual_override, ch0_pd, ch1_pd).eq(self.dac_ctrl.storage),
-            dac_pads.rst.eq(ResetSignal("sys")),
+            dac_pads.rst.eq(ResetSignal("dco2d")),
             dac_afe_pads.ch1_pd_n.eq(~ch0_pd),
             dac_afe_pads.ch2_pd_n.eq(~ch1_pd),
             output_data_ch0.eq(
-                Mux(manual_override, self.output_value_ch0.storage, self.data_in[0])
+                Mux(manual_override, self.data_in_csr_cdc[0], self.data_in_cdc[0])
             ),
             output_data_ch1.eq(
-                Mux(manual_override, self.output_value_ch1.storage, self.data_in[1])
+                Mux(manual_override, self.data_in_csr_cdc[1], self.data_in_cdc[1])
             ),
         ]
 
-        # data
+        self.specials += [
-        for lane in range(14):
+            Instance("ODDR", 
-            self.specials += DDROutput(
+                i_C=ClockSignal("dco2d"), 
-                i1 = output_data_ch0[lane], 
+                i_CE=~ResetSignal("dco2d"), 
-                i2 = output_data_ch1[lane], 
+                i_D1=output_data_ch0[lane], # DDR CLK Rising Edge
-                o = dac_pads.data[lane], 
+                i_D2=output_data_ch1[lane], # DDR CLK Falling Edge
-                clk = ClockSignal("dco2d")
+                o_Q=dac_pads.data[lane],
-            )
+                p_DDR_CLK_EDGE="SAME_EDGE") 
-        
+            for lane in range(14)]
-        # clock forwarding
+        self.specials += Instance("ODDR", 
-        self.specials += DDROutput(
+                i_C=ClockSignal("dco2d_45_degree"), 
-            i1 = 0b0,
+                i_CE=~ResetSignal("dco2d"), 
-            i2 = 0b1,
+                i_D1=0, 
-            o = dac_pads.dclkio,
+                i_D2=1, 
-            clk = ClockSignal("dco2d"),
+                o_Q=dac_pads.dclkio,
-        )
+                p_DDR_CLK_EDGE="SAME_EDGE")
 
 
 class AUX_DAC_CTRL(Module, AutoCSR):

fast-servo/linien-gateware/fast_servo_soc.py

@@ -147,6 +147,7 @@ class BaseSoC(PS7, AutoCSR):
         # self.add_main_adc(platform)
         self.submodules.adc = ADC(platform)
         self.csr_devices.append("adc")
+        platform.add_false_path_constraints(self.crg.cd_sys.clk, self.adc.crg.cd_dco2d.clk)
 
         # self.add_main_dac(platform)
         self.submodules.dac = DAC(platform)

fast-servo/linien-pyrp3-monitor.patch

@@ -0,0 +1,141 @@
+# Fix for bus error issues when compiling cpython extensions in pyrp3 v1.2.0+
+# Patch sourced from: https://github.com/linien-org/pyrp3/tree/e6688acf8bd79d2dbe1d192d09c1a1baf1f6c67b (setup.py & monitor/Makefile)
+# Reference: https://github.com/elhep/Fast-Servo-Firmware/blob/master/OS/scripts/linien_install_requirements.sh#L28
+
+diff --git a/monitor/Makefile b/monitor/Makefile
+new file mode 100644
+index 0000000..044d88e
+--- /dev/null
++++ b/monitor/Makefile
+@@ -0,0 +1,31 @@
++# Makefile for libmonitor
++
++OBJS = monitor.o
++SRCS = $(subst .o,.c, $(OBJS))
++OSOBJS = monitor.os
++TARGETLIB=libmonitor.so
++CFLAGS=-g -std=gnu99 -Wall -Werror
++LIBS=-lm -lpthread
++
++# Use CROSS_COMPILE=arm-linux-gnueabi-
++CC=$(CROSS_COMPILE)gcc
++INSTALL_DIR ?= .
++
++
++all: $(TARGETLIB)
++lib: $(TARGETLIB)
++
++%.os: %.c
++	$(CC) -c -fPIC $(CFLAGS) $< -o $@
++
++$(TARGETLIB): $(OSOBJS)
++	$(CC) -o $@ -shared $^ $(CFLAGS) $(LIBS)
++
++clean:
++	rm -f $(TARGETLIB) *.o *.os
++
++# Install target - creates 'lib/' sub-directory in $(INSTALL_DIR) and copies all
++# executables to that location.
++install:
++	mkdir -p $(INSTALL_DIR)/lib
++	cp $(TARGETLIB) $(INSTALL_DIR)/lib
+\ No newline at end of file
+diff --git a/pyrp3/raw_memory.py b/pyrp3/raw_memory.py
+index ce1b28e..233b82a 100644
+--- a/pyrp3/raw_memory.py
++++ b/pyrp3/raw_memory.py
+@@ -1,12 +1,9 @@
+ from ctypes import POINTER, c_uint32, cast, cdll, create_string_buffer, sizeof
+-from importlib.machinery import EXTENSION_SUFFIXES
+ from pathlib import Path
+ 
+ import numpy as np
+ 
+-libmonitor_file = str(
+-    Path(__file__).parent / ".." / "monitor{}".format(EXTENSION_SUFFIXES[0])
+-)
++libmonitor_file = 'libmonitor.so'
+ 
+ libmonitor = cdll.LoadLibrary(libmonitor_file)
+ libmonitor.read_value.restype = c_uint32
+diff --git a/setup.py b/setup.py
+index 98bdaee..b0a8af4 100644
+--- a/setup.py
++++ b/setup.py
+@@ -1,5 +1,10 @@
+ import re
+-from distutils.core import Extension, setup
++import os
++
++from distutils.core import setup
++from distutils.command.build import build
++from distutils.command.install import install
++
+ from pathlib import Path
+ 
+ # from https://stackoverflow.com/a/7071358/2750945
+@@ -11,9 +16,50 @@ if mo:
+     verstr = mo.group(1)
+ else:
+     raise RuntimeError("Unable to find version string in %s." % (VERSIONFILE,))
++
++# Patch from https://github.com/linien-org/pyrp3/blob/e6688acf8bd79d2dbe1d192d09c1a1baf1f6c67b/setup.py#L16-L55
++build_dir = "monitor/"
++
++def compile_libmonitor():
++    cwd = os.getcwd()  # get current directory
++    try:
++        os.chdir(build_dir)
++        os.system("make clean")
++        os.system("make all")
++    finally:
++        os.chdir(cwd)
++
++
++def install_libmonitor(prefix=""):
++    cwd = os.getcwd()  # get current directory
++    try:
++        os.chdir(build_dir)
++        os.system("make install INSTALL_DIR={prefix}".format(prefix=prefix))
++    finally:
++        os.chdir(cwd)
++
++
++class lib_build(build):
++    def run(self):
++        compile_libmonitor()
++        build.run(self)
++
++
++class lib_install(install):
++    def run(self):
++        compile_libmonitor()
++        install_libmonitor(self.prefix)
++        # install.run(self)
++
++# Will use nix to install libmonitor
++cmdclass = {
++    "build": lib_build
++}
++
+ this_directory = Path(__file__).parent
+ long_description = (this_directory / "README.rst").read_text()
+ 
++
+ setup(
+     name="pyrp3",
+     version=verstr,
+@@ -32,6 +78,7 @@ setup(
+         "cached_property>=1.5.2",
+         "numpy>=1.11.0",
+     ],
++    cmdclass=cmdclass,
+     classifiers=[
+         "Intended Audience :: Developers",
+         "Intended Audience :: Education",
+@@ -45,5 +92,4 @@ setup(
+         "Topic :: Software Development :: Libraries :: Python Modules",
+     ],
+     keywords=["redpitaya", "FPGA", "zynq"],
+-    ext_modules=[Extension("monitor", ["monitor/monitor.c"])],
+ )

fast-servo/pyfastservo/README.md

@@ -0,0 +1,5 @@
+## Source Repository
+Files in this directory were copied from [elhep/Fast-Servo-Firmware](https://github.com/elhep/Fast-Servo-Firmware/tree/master/fast_servo/pythonscripts).
+
+## Commit ID
+The files were copied from commit ID [7fae40c](https://github.com/elhep/Fast-Servo-Firmware/commit/7fae40c0f872a91218be378f8289b98b1e366729).

fast-servo/pyfastservo/adc.py

@@ -0,0 +1,224 @@
+# This file is part of Fast Servo Software Package.
+#
+# Copyright (C) 2023 Jakub Matyas
+# Warsaw University of Technology <jakubk.m@gmail.com>
+# SPDX-License-Identifier: GPL-3.0-or-later
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+# 
+# This program is distributed in the hope that it will be useful, 
+# but WITHOUT ANY WARRANTY; without even the implied warranty of 
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <https://www.gnu.org/licenses/>.
+
+import time
+import spidev
+from pyfastservo.common import (
+    ADC_AFE_CTRL_ADDR,
+    ADC_BITSLIP_ADDR,
+    ADC_CH0_HIGH_ADDR,
+    ADC_CH0_LOW_ADDR,
+    ADC_CH1_HIGH_ADDR,
+    ADC_CH1_LOW_ADDR,
+    ADC_DELAY_ADDR,
+    ADC_FRAME_ADDR,
+    AUX_ADC_ADDR,
+    MAP_MASK,
+    PAGESIZE,
+    write_to_memory,
+    read_from_memory
+)
+
+# /dev/spidev1.0  <=> spidev<BUS>.<DEVICE>
+MAIN_ADC_BUS = 1
+MAIN_ADC_DEVICE = 1
+
+AUX_ADC_BUS = 1
+AUX_ADC_PORT_A = 2
+AUX_ADC_PORT_B = 3
+
+
+def spi_write(spi, address, value):
+    spi.xfer2([address, value])
+
+def spi_read(spi, address):
+    rx_buffer = spi.xfer2([0x80 | address, 0x00])
+    return rx_buffer[1]
+
+def main_adc_config(spi, test_pattern):
+    high_word = (test_pattern & 0xFF00) >> 8
+    low_word = test_pattern & 0xFF
+
+    spi_write(spi, 0x00, 0x80)              # reset
+    spi_write(spi, 0x01, 0x20)              # REGISTER A1: set to Two's complement Data Format
+    spi_write(spi, 0x02, 0x15)              # REGISTER A2: set to LVDS output, set 4 data lanes and turn on test mode
+    spi_write(spi, 0x03, high_word)         # REGISTER A3: test pattern high word
+    spi_write(spi, 0x04, low_word)          # REGISTER A4: test pattern low word
+
+def main_adc_test_mode(spi, enable):
+    reg_contents = 0x15 if enable else 0x11 # set to LVDS output, set 4 data lanes and turn on or off test mode
+    spi_write(spi, 0x02, reg_contents)
+
+def verify_adc_registers(spi, reg_to_check):
+    for register, expected_value in reg_to_check.items():
+        value = spi_read(spi, register)
+        print(f"Spi readback register 0x{register:02x}: 0x{value:02x}")
+        if value != expected_value:
+            print(f"Different value read than sent in reg 0x{register:02x}")
+
+def read_frame():
+    return read_from_memory(ADC_FRAME_ADDR, 1)[0]
+
+def perform_bitslip():
+    for i in range(4):
+        current_frame = read_frame()
+        if current_frame & 0x0F != 0x0C:
+            print(f"Performing bitslip (iteration: {i}). Current frame: 0x{current_frame:02x}")
+            write_to_memory(ADC_BITSLIP_ADDR, 1)
+        else:
+            print(f"No bitslip required; Current frame: 0x{current_frame:02x}")
+            return
+
+def mmcm_rst():
+    curr_cfg = read_from_memory(ADC_AFE_CTRL_ADDR, 1)[0] & 0x0F
+    write_to_memory(ADC_AFE_CTRL_ADDR, 0x10 | curr_cfg) # Reset MMCM
+    write_to_memory(ADC_AFE_CTRL_ADDR, 0x00 | curr_cfg) # Release MMCM Reset
+    while not(read_frame() & 0x10):
+        print(f"Waiting for MMCM to lock")
+        time.sleep(0.001)
+
+def inc_ddr_clk_phase():
+    curr_cfg = read_from_memory(ADC_AFE_CTRL_ADDR, 1)[0] & 0x1F
+    write_to_memory(ADC_AFE_CTRL_ADDR, 0x40 | curr_cfg) # Set MMCM Phase Shift to be INC
+    write_to_memory(ADC_AFE_CTRL_ADDR, 0x60 | curr_cfg) # Assert MMCM Phase Shift EN High
+    write_to_memory(ADC_AFE_CTRL_ADDR, curr_cfg)        # Deassert MMCM Phase Shift EN High
+
+def dec_ddr_clk_phase():
+    curr_cfg = read_from_memory(ADC_AFE_CTRL_ADDR, 1)[0] & 0x1F
+    write_to_memory(ADC_AFE_CTRL_ADDR, 0x00 | curr_cfg) # Set MMCM Phase Shift to be DEC
+    write_to_memory(ADC_AFE_CTRL_ADDR, 0x20 | curr_cfg) # Assert MMCM Phase Shift EN High
+    write_to_memory(ADC_AFE_CTRL_ADDR, curr_cfg)        # Deassert MMCM Phase Shift EN High
+
+def find_edge():
+    prev_frame = read_frame()
+    for tap_delay in range(32):
+        write_to_memory(ADC_DELAY_ADDR, tap_delay)
+        current_frame = read_frame()
+
+        print(f"Tap delay: {tap_delay}, Current frame: 0x{current_frame:02x}")
+        print(f"prev_frame: 0x{prev_frame:02x}")
+
+        if current_frame != prev_frame:
+            final_delay = ((tap_delay+1) // 2) + 2
+            print(f"Edge detected; setting iDelay to: {final_delay}")
+            write_to_memory(ADC_DELAY_ADDR, final_delay)
+            return
+
+        prev_frame = current_frame
+
+    # If no edge detected
+    final_delay = 11
+    print(f"No edge detected; setting iDelay to: {final_delay}")
+    write_to_memory(ADC_DELAY_ADDR, final_delay)
+
+def read_adc_channel(high_addr, low_addr):
+    return (read_from_memory(high_addr, 1)[0] << 8) | read_from_memory(low_addr, 1)[0]
+
+def print_adc_channels():
+    adc_ch0 = read_adc_channel(ADC_CH0_HIGH_ADDR, ADC_CH0_LOW_ADDR)
+    adc_ch1 = read_adc_channel(ADC_CH1_HIGH_ADDR, ADC_CH1_LOW_ADDR)
+    print(f"Final ADC_CH0: 0x{adc_ch0:04x}")
+    print(f"Final ADC_CH1: 0x{adc_ch1:04x}")
+
+def enable_adc_afe(ch1_x10=False, ch2_x10=False):
+    ctrl_value = (ch2_x10 << 1) | ch1_x10
+    write_to_memory(ADC_AFE_CTRL_ADDR, ctrl_value)
+    afe_ctrl = read_from_memory(ADC_AFE_CTRL_ADDR, 1)[0]
+    print(f"ADC_AFE_CTRL: 0x{afe_ctrl:02X}")
+    return afe_ctrl
+
+def search_edge():
+    for tap_delay in range(32):
+        print(f"iDelay to: {tap_delay}")
+        write_to_memory(ADC_DELAY_ADDR, tap_delay)
+        time.sleep(1)
+        current_frame = read_frame()
+        print(f"Tap delay: {tap_delay}, Current frame: 0x{current_frame:02x}")
+        print_adc_channels()
+
+def print_adc_channel(ch):
+    if ch == 0:
+        adc_ch0 = read_adc_channel(ADC_CH0_HIGH_ADDR, ADC_CH0_LOW_ADDR)
+        print(f"Final ADC_CH0: 0x{adc_ch0:04x}")
+    if ch == 1:
+        adc_ch1 = read_adc_channel(ADC_CH1_HIGH_ADDR, ADC_CH1_LOW_ADDR)
+        print(f"Final ADC_CH1: 0x{adc_ch1:04x}")
+
+def find_min_max_ch(ch):
+    test = []
+    for i in range(100):
+        if ch == 0:
+            test.append(read_adc_channel(ADC_CH0_HIGH_ADDR, ADC_CH0_LOW_ADDR))
+        else:
+            test.append(read_adc_channel(ADC_CH1_HIGH_ADDR, ADC_CH1_LOW_ADDR)) 
+        print("ch", ch, hex(test[-1]))
+    print("Min:", hex(min(test)))
+    print("Max:", hex(max(test)))
+    print("Diff:", hex(max(test)-min(test)))
+
+
+def configure_ltc2195():
+    spi = spidev.SpiDev()
+    try:
+        spi.open(MAIN_ADC_BUS, MAIN_ADC_DEVICE)
+        spi.max_speed_hz = 50000
+        spi.mode = 0b00  # CPOL = 0 CPHA = 0
+        spi.cshigh = False
+
+        test_pattern = 0x811F
+        main_adc_config(spi, test_pattern)
+
+        verify_adc_registers(spi, {
+            0x01: 0x20,
+            0x02: 0x15,
+            0x03: (test_pattern & 0xFF00) >> 8,
+            0x04: test_pattern & 0xFF
+        })
+
+        # ADC software reset put its PLL to sleep momentarily. Thus, MMCM needs to be reset as well.
+        mmcm_rst()
+        
+        # Performing Word Align
+        perform_bitslip()
+        find_edge()
+        
+        # Printing it once is not enough to check whether the alignment is correct.
+        for i in range(100):
+            print_adc_channels()
+
+        main_adc_test_mode(spi, False)
+        verify_adc_registers(spi, {0x02: 0x11})  # Verify test mode is off
+      
+        # FIXME: AFE Gain 1x is not functional on that batch of fast servo under development
+        enable_adc_afe(ch1_x10=1, ch2_x10=1)
+
+        #find_min_max_ch(0)
+        #find_min_max_ch(1)
+
+        #for i in range(10):
+        #    print_adc_channel(0)
+
+        #for i in range(10):
+        #    print_adc_channel(1)
+
+    finally:
+        spi.close()
+
+if __name__ == "__main__":
+    configure_ltc2195()

fast-servo/pyfastservo/common.py

@@ -0,0 +1,120 @@
+# This file is part of Fast Servo Software Package.
+#
+# Copyright (C) 2023 Jakub Matyas
+# Warsaw University of Technology <jakubk.m@gmail.com>
+# SPDX-License-Identifier: GPL-3.0-or-later
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+# 
+# This program is distributed in the hope that it will be useful, 
+# but WITHOUT ANY WARRANTY; without even the implied warranty of 
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <https://www.gnu.org/licenses/>.
+
+import os
+import mmap
+
+CSR_SIZE = 0x800
+MAP_SIZE = 0x1000
+MAP_MASK = 0xFFF
+PAGESIZE = 0x1000
+
+# LINIEN_OFFSET = 0x0
+LINIEN_OFFSET = 0x300000
+
+# ----------------------------------------------------------------
+# FRONT PANEL LEDS REGISTER ADDRESSES
+LED0_BASE_ADDR = 0x40005000 + LINIEN_OFFSET
+LED1_BASE_ADDR = 0x40005800 + LINIEN_OFFSET
+LED2_BASE_ADDR = 0x40006000 + LINIEN_OFFSET
+LED3_BASE_ADDR = 0x40006800 + LINIEN_OFFSET
+
+
+# ----------------------------------------------------------------
+# DAC REGISTER ADDRESSES
+ADC_BASE_ADDR            =      0x40004800 + LINIEN_OFFSET
+ADC_FRAME_OFFSET         =      0x0
+ADC_CH0_HIGH_OFFSET      =      0x4
+ADC_CH0_LOW_OFFSET       =      0x8
+ADC_CH1_HIGH_OFFSET      =      0xC
+ADC_CH1_LOW_OFFSET       =      0x10
+ADC_TAP_DELAY_OFFSET     =      0x14
+ADC_BITSLIP_OFFSET       =      0x18
+ADC_AFE_CTRL_OFFSET     =       0x1C
+
+
+ADC_FRAME_ADDR      =   ADC_BASE_ADDR + ADC_FRAME_OFFSET
+ADC_CH0_HIGH_ADDR   =   ADC_BASE_ADDR + ADC_CH0_HIGH_OFFSET
+ADC_CH0_LOW_ADDR    =   ADC_BASE_ADDR + ADC_CH0_LOW_OFFSET
+ADC_CH1_HIGH_ADDR   =   ADC_BASE_ADDR + ADC_CH1_HIGH_OFFSET
+ADC_CH1_LOW_ADDR    =   ADC_BASE_ADDR + ADC_CH1_LOW_OFFSET
+ADC_DELAY_ADDR      =   ADC_BASE_ADDR + ADC_TAP_DELAY_OFFSET
+ADC_BITSLIP_ADDR    =   ADC_BASE_ADDR + ADC_BITSLIP_OFFSET
+ADC_AFE_CTRL_ADDR   =   ADC_BASE_ADDR + ADC_AFE_CTRL_OFFSET
+
+AUX_ADC_ADDR        =   0x40007800 + LINIEN_OFFSET
+
+
+# ----------------------------------------------------------------
+# DAC REGISTER ADDRESSES
+DAC_BASE_ADDR           =   0x40007000 + LINIEN_OFFSET
+CTRL_OFFSET             =   0x0
+CH0_HIGH_WORD_OFFSET    =   0x4
+CH0_LOW_WORD_OFFSET     =   0x8
+CH1_HIGH_WORD_OFFSET    =   0xC
+CH1_LOW_WORD_OFFSET     =   0x10
+
+CTRL_ADDR               =   DAC_BASE_ADDR + CTRL_OFFSET
+CH0_HIGH_WORD_ADDR      =   DAC_BASE_ADDR + CH0_HIGH_WORD_OFFSET
+CH0_LOW_WORD_ADDR       =   DAC_BASE_ADDR + CH0_LOW_WORD_OFFSET
+CH1_HIGH_WORD_ADDR      =   DAC_BASE_ADDR + CH1_HIGH_WORD_OFFSET
+CH1_LOW_WORD_ADDR       =   DAC_BASE_ADDR + CH1_LOW_WORD_OFFSET
+
+
+def read_from_memory(address, n_bytes):
+    assert n_bytes <= 4
+    addr = address
+
+    try:
+        f = os.open("/dev/mem", os.O_SYNC | os.O_RDWR)
+        with mmap.mmap(
+            f,
+            PAGESIZE,
+            mmap.MAP_SHARED,
+            mmap.PROT_READ | mmap.PROT_WRITE,
+            offset=addr & ~MAP_MASK,
+        ) as mem:
+            start_addr = addr & MAP_MASK
+            stop_addr = start_addr + 4
+            contents = mem[start_addr:stop_addr]
+            read_value = list(contents)[:n_bytes]
+    finally:
+        os.close(f)
+
+    return read_value
+
+def write_to_memory(address, value):
+    value_bytes = value.to_bytes(4, "little")
+    addr = address
+
+    try:
+        f = os.open("/dev/mem", os.O_SYNC | os.O_RDWR)
+        with mmap.mmap(
+            f,
+            PAGESIZE,
+            mmap.MAP_SHARED,
+            mmap.PROT_READ | mmap.PROT_WRITE,
+            offset=addr & ~MAP_MASK,
+        ) as mem:
+            start_addr = addr & MAP_MASK
+            stop_addr = start_addr + 4
+            mem[start_addr:stop_addr] = value_bytes
+            contents = mem[start_addr:stop_addr]
+    finally:
+        os.close(f)

fast-servo/pyfastservo/dac.py

@@ -0,0 +1,168 @@
+# This file is part of Fast Servo Software Package.
+#
+# Copyright (C) 2023 Jakub Matyas
+# Warsaw University of Technology <jakubk.m@gmail.com>
+# SPDX-License-Identifier: GPL-3.0-or-later
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+# 
+# This program is distributed in the hope that it will be useful, 
+# but WITHOUT ANY WARRANTY; without even the implied warranty of 
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <https://www.gnu.org/licenses/>.
+
+import time
+
+import spidev
+from pyfastservo.common import (
+    CH0_HIGH_WORD_ADDR,
+    CH0_LOW_WORD_ADDR,
+    CH1_HIGH_WORD_ADDR,
+    CH1_LOW_WORD_ADDR,
+    CTRL_ADDR,
+    MAP_MASK,
+    PAGESIZE,
+    write_to_memory,
+    read_from_memory
+)
+
+# /dev/spidev2.0  <=> spidev<BUS>.<DEVICE>
+MAIN_DAC_BUS = 2
+MAIN_DAC_DEVICE = 0
+DAC_VERSION = 0x0A
+
+
+def spi_write(spi, address, value):
+    spi.xfer2([address, value])
+
+def spi_read(spi, address):
+    rx_buffer = spi.xfer2([0x80 | address, 0x00])
+    return rx_buffer[1]
+
+def soft_reset(spi):
+    spi_write(spi, 0x00, 0x10)  # Software reset
+    spi_write(spi, 0x00, 0x00)  # Release software reset
+    spi_read(spi, 0x00)         # Read reset address (necessary for reset to take effect)
+
+def check_version(spi):
+    version = spi_read(spi, 0x1F)
+    print(f"DAC version: 0x{version:02X}")
+    return version == DAC_VERSION
+
+def configure_dac(spi):
+    power_down_reg = spi_read(spi, 0x01)
+    spi_write(spi, 0x01, power_down_reg & ~(1 << 0))  # Clear EXTREF bit for internal reference
+    spi_write(spi, 0x0D, 0x00)      # Set RREF to 10 kΩ for 1.0V reference
+    spi_write(spi, 0x04, 0xA0)      # Enable on-chip IRSET (1.6 kΩ for 20mA output)
+    spi_write(spi, 0x07, 0xA0)      # Enable on-chip QRSET (1.6 kΩ for 20mA output)
+    spi_write(spi, 0x05, 0x00)      # Disable internal IRCML
+    spi_write(spi, 0x08, 0x00)      # Disable internal QRCML
+    spi_write(spi, 0x02, 0xB4)      # Enable 2's complement, IFirst: True, IRising: True, DCI_EN: Enabled
+    spi_write(spi, 0x14, 0x00)      
+    spi_write(spi, 0x14, 0x08)      # Trigger the retimer to reacquire the clock relationship
+    spi_write(spi, 0x14, 0x00)
+
+def dac_self_calibration(spi):
+    spi_write(spi, 0x12, 0x00)      # Reset calibration status
+    spi_write(spi, 0x0E, 0x08)      # Enable calibration clock, default divide ratio
+    spi_write(spi, 0x0E, 0x38)      # CALSELI = 1, CALSELQ = 1, CALCLK = 1
+    spi_write(spi, 0x12, 0x10)      # Set CALEN bit
+
+    while True:
+        status = spi_read(spi, 0x0F)
+        if status & 0xC0 == 0xC0:   # Both CALSTATI and CALSTATQ are 1
+            break
+        time.sleep(0.01)
+
+    spi_write(spi, 0x12, 0x00)      # Clear calibration bits
+    spi_write(spi, 0x0E, 0x30)      # Keep CALSELI and CALSELQ set, clear CALCLK
+    print("DAC self-calibration completed")
+
+def manual_override(enable=True):
+    reg_contents = read_from_memory(CTRL_ADDR, 1)[0]
+    to_write = reg_contents | 0b1 if enable else reg_contents & 0b110
+    write_to_memory(CTRL_ADDR, to_write)
+    print(f"Set DAC Output Manual Override: {enable}")
+
+def power_down_afe(channel, power_down=True):
+    assert channel in (0, 1)
+
+    bitmask = 1 << (channel + 1) & 0b111
+    reg_contents = read_from_memory(CTRL_ADDR, 1)[0]
+    value = (1 if power_down else 0) << (channel + 1)
+    reg_contents &= ~bitmask
+
+    to_write = reg_contents | value
+    write_to_memory(CTRL_ADDR, to_write)
+    reg_contents = read_from_memory(CTRL_ADDR, 1)[0]
+    print(f"Power Down DAC AFE Ch{channel}: {power_down}")
+
+def set_dac_output(value):
+    value = min(value, 0x3FFF)
+    low_word = value & 0xFF
+    high_word = (value >> 8) & 0x3F
+
+    # Note: DAC HIGH word and LOW word output are not updated 
+    #   at the same time. On scope, you will see more than one step
+    #   of value changed.
+    write_to_memory(CH0_HIGH_WORD_ADDR, high_word)
+    write_to_memory(CH0_LOW_WORD_ADDR, low_word)
+    write_to_memory(CH1_HIGH_WORD_ADDR, high_word)
+    write_to_memory(CH1_LOW_WORD_ADDR, low_word)
+    print(f"DAC output set to: 0x{value:04X}")
+
+def check_clk_relationship(spi):
+    clkmode_reg = spi_read(spi, 0x14)
+    print(f"CLKMODE reg: 0x{clkmode_reg:02X}")
+    if clkmode_reg & 0b00010000:
+        print("Clock relationship is not found")
+        return False
+    else:
+        print("Clock relationship is found")
+        return True
+
+def configure_ad9117():
+    spi = spidev.SpiDev()
+    spi.open(MAIN_DAC_BUS, MAIN_DAC_DEVICE)
+    spi.max_speed_hz = 5000
+    spi.mode = 0b00  # CPOL = 0 CPHA = 0
+    spi.cshigh = False
+
+    try:
+        soft_reset(spi)
+        if not check_version(spi):
+            print("Unrecognized DAC version")
+            return False
+
+        power_down_afe(0, True)
+        power_down_afe(1, True)
+
+        configure_dac(spi)
+        check_clk_relationship(spi)
+        dac_self_calibration(spi)
+
+        # Enable DAC outputs
+        spi_write(spi, 0x01, spi_read(spi, 0x01) & ~((1 << 4) | (1 << 3)))
+
+        power_down_afe(0, False)
+        power_down_afe(1, False)
+        manual_override(False)
+
+        print("AD9117 configuration completed successfully")
+        return True
+
+    except Exception as e:
+        print(f"Error configuring AD9117: {e}")
+        return False
+
+    finally:
+        spi.close()
+
+if __name__ == "__main__":
+    configure_ad9117()

fast-servo/pyfastservo/fp_leds.py

@@ -0,0 +1,66 @@
+# This file is part of Fast Servo Software Package.
+#
+# Copyright (C) 2023 Jakub Matyas
+# Warsaw University of Technology <jakubk.m@gmail.com>
+# SPDX-License-Identifier: GPL-3.0-or-later
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+# 
+# This program is distributed in the hope that it will be useful, 
+# but WITHOUT ANY WARRANTY; without even the implied warranty of 
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <https://www.gnu.org/licenses/>.
+
+import mmap
+import os
+import time
+
+from pyfastservo.common import (
+    LED0_BASE_ADDR,
+    LED1_BASE_ADDR,
+    LED2_BASE_ADDR,
+    LED3_BASE_ADDR,
+    MAP_MASK,
+    PAGESIZE,
+)
+
+ON = 1
+OFF = 0
+
+
+def main():
+    addrs = [LED0_BASE_ADDR, LED1_BASE_ADDR, LED2_BASE_ADDR, LED3_BASE_ADDR]
+
+    f = os.open("/dev/mem", os.O_SYNC | os.O_RDWR)
+    for addr in addrs:
+        with mmap.mmap(
+            f,
+            PAGESIZE,
+            mmap.MAP_SHARED,
+            mmap.PROT_READ | mmap.PROT_WRITE,
+            offset=addr & ~MAP_MASK,
+        ) as mem:
+            for i in range(6):
+                start_addr = addr & MAP_MASK
+                stop_addr = start_addr + 4
+                print(
+                    f"addr: 0x{addr:x}\tstart_addr: 0x{start_addr}\tstop_addr: 0x{stop_addr}"
+                )
+                mem[start_addr:stop_addr] = ON.to_bytes(4, "little")
+                contents = mem[start_addr:stop_addr]
+                time.sleep(0.5)
+                mem[start_addr:stop_addr] = OFF.to_bytes(4, "little")
+                contents = mem[start_addr:stop_addr]
+                time.sleep(0.5)
+
+    os.close(f)
+
+
+if __name__ == "__main__":
+    main()

fast-servo/pyfastservo/initialize.py

@@ -0,0 +1,28 @@
+# This file is part of Fast Servo Software Package.
+#
+# Copyright (C) 2023 Jakub Matyas
+# Warsaw University of Technology <jakubk.m@gmail.com>
+# SPDX-License-Identifier: GPL-3.0-or-later
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+# 
+# This program is distributed in the hope that it will be useful, 
+# but WITHOUT ANY WARRANTY; without even the implied warranty of 
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <https://www.gnu.org/licenses/>.
+
+from pyfastservo import adc, si5340, dac
+
+def main():
+    si5340.configure_si5340()
+    adc.configure_ltc2195()
+    dac.configure_ad9117()
+
+if __name__ == "__main__":
+    main()

fast-servo/pyfastservo/si5340.py

@@ -0,0 +1,280 @@
+# This file is part of Fast Servo Software Package.
+#
+# Copyright (C) 2023 Jakub Matyas
+# Warsaw University of Technology <jakubk.m@gmail.com>
+# SPDX-License-Identifier: GPL-3.0-or-later
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+# 
+# This program is distributed in the hope that it will be useful, 
+# but WITHOUT ANY WARRANTY; without even the implied warranty of 
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <https://www.gnu.org/licenses/>.
+
+# Additional Reference:
+# https://github.com/torvalds/linux/blob/master/drivers/clk/clk-si5341.c
+
+import time
+from smbus2 import SMBus
+
+BUS_NO = 0
+IC_ADDR = 0x74
+
+DEVICE_READY = 0x00FE
+PLL_M_DEN = 0x023B
+STATUS = 0x000C
+STATUS_STICKY = 0x0011
+
+STATUS_LOSREF = 0x04
+STATUS_LOL = 0x08
+
+
+def write_register(bus, address, value):
+    page = address >> 8
+    register = address & 0xFF
+    bus.write_byte_data(IC_ADDR, 0x01, page)
+    try:
+        bus.write_byte_data(IC_ADDR, register, value)
+    except Exception as e:
+        raise Exception(f"Write failed 0x{value:02X} at 0x{address:04X}: {e}")
+
+def write_preamble(bus):
+    preamble = [
+        (0x0B24, 0xC0),
+        (0x0B25, 0x00),
+        (0x0502, 0x01),
+        (0x0505, 0x03),
+        (0x0957, 0x17),
+        (0x0B4E, 0x1A),
+    ]
+    for address, value in preamble:
+        write_register(bus, address, value)
+
+def write_postamble(bus):
+    postamble = [
+        (0x001C, 0x01),  # Soft reset
+        (0x0B24, 0xC3),
+        (0x0B25, 0x02),
+    ]
+    for address, value in postamble:
+        write_register(bus, address, value)
+
+def wait_device_ready(bus):
+    for _ in range(15):
+        if bus.read_byte_data(IC_ADDR, DEVICE_READY) == 0x0F:
+            return True
+        time.sleep(0.02)
+    return False
+
+def wait_for_lock(bus):
+    for _ in range(10):
+        status = bus.read_byte_data(IC_ADDR, STATUS)
+        if not (status & (STATUS_LOSREF | STATUS_LOL)):
+            return True
+        time.sleep(0.01)
+    return False
+
+def check_pll_status(bus):
+    pll_status = bus.read_byte_data(IC_ADDR, 0x0C)
+    pll_locked = not (pll_status & STATUS_LOL)
+    print(f"PLL {'locked' if pll_locked else 'unlocked'}")
+    return pll_locked
+
+def check_los_status(bus):
+    los_status = bus.read_byte_data(IC_ADDR, 0x0D)
+    xaxb_los = (los_status & 0x10) != 0
+    print(f"XA/XB LOS {'asserted' if xaxb_los else 'deasserted'}")
+    return not xaxb_los
+
+def configure_si5340():
+    with SMBus(BUS_NO) as bus:
+        if not wait_device_ready(bus):
+            print("Device not ready. Aborting.")
+            return
+
+        # Programming sequence from ClockBuilder Pro, default settings
+        # to initialize system using XTAL input
+        main_config = [
+            (0x0006, 0x00),  # TOOL_VERSION
+            (0x0007, 0x00),  # Not in datasheet
+            (0x0008, 0x00),  # Not in datasheet
+            (0x000B, 0x74),  # I2C_ADDR
+            (0x0017, 0xD0),  # INT mask (disable interrupts)
+            (0x0018, 0xFF),  # INT mask
+            (0x0021, 0x0F),  # Select XTAL as input
+            (0x0022, 0x00),  # Not in datasheet
+            (0x002B, 0x02),  # SPI config
+            (0x002C, 0x20),  # LOS enable for XTAL
+            (0x002D, 0x00),  # LOS timing
+            (0x002E, 0x00),  # LOS trigger (thresholds)
+            (0x002F, 0x00),
+            (0x0030, 0x00),
+            (0x0031, 0x00),
+            (0x0032, 0x00),
+            (0x0033, 0x00),
+            (0x0034, 0x00),
+            (0x0035, 0x00),  # LOS trigger (thresholds) end
+            (0x0036, 0x00),  # LOS clear (thresholds)
+            (0x0037, 0x00),
+            (0x0038, 0x00),
+            (0x0039, 0x00),
+            (0x003A, 0x00),
+            (0x003B, 0x00),
+            (0x003C, 0x00),
+            (0x003D, 0x00),  # LOS clear (thresholds) end
+            (0x0041, 0x00),  # LOS0_DIV_SEL
+            (0x0042, 0x00),  # LOS1_DIV_SEL
+            (0x0043, 0x00),  # LOS2_DIV_SEL
+            (0x0044, 0x00),  # LOS3_DIV_SEL
+            (0x009E, 0x00),  # LOL_SET_THR
+            (0x0102, 0x01),  # Enable outputs
+            (0x013F, 0x00),  # OUTX_ALWAYS_ON
+            (0x0140, 0x00),  # OUTX_ALWAYS_ON
+            (0x0141, 0x40),  # OUT_DIS_LOL_MSK, OUT_DIS_MSK_LOS_PFD
+            (0x0202, 0x00),  # XAXB_FREQ_OFFSET (=0)
+
+            # PLL Configuration
+            (0x0235, 0x00),  # M_NUM
+            (0x0236, 0x00),
+            (0x0237, 0x00),
+            (0x0238, 0x80),
+            (0x0239, 0x89),
+            (0x023A, 0x00),
+            (0x023B, 0x00),  # M_DEN
+            (0x023C, 0x00),
+            (0x023D, 0x00),
+            (0x023E, 0x80),
+
+            # Synthesizer configuration
+            (0x0302, 0x00),  # N0_NUM
+            (0x0303, 0x00),
+            (0x0304, 0x00),
+            (0x0305, 0x00),
+            (0x0306, 0x21),
+            (0x0307, 0x00),
+            (0x0308, 0x00),  # N0_DEN
+            (0x0309, 0x00),
+            (0x030A, 0x00),
+            (0x030B, 0x80),
+            (0x030C, 0x01), # N0_UPDATE
+
+            # N1 Configuration (1:1 ratio)
+            (0x030D, 0x00),  # N1_NUM
+            (0x030E, 0x00),
+            (0x030F, 0x00),
+            (0x0310, 0x00),
+            (0x0311, 0x00),
+            (0x0312, 0x01),
+            (0x0313, 0x00),  # N1_DEN
+            (0x0314, 0x00),
+            (0x0315, 0x00),
+            (0x0316, 0x01),
+            (0x0317, 0x01),  # N1_UPDATE
+
+            # N2 Configuration (1:1 ratio)
+            (0x0318, 0x00),  # N2_NUM
+            (0x0319, 0x00),
+            (0x031A, 0x00),
+            (0x031B, 0x00),
+            (0x031C, 0x00),
+            (0x031D, 0x01),
+            (0x031E, 0x00),  # N2_DEN
+            (0x031F, 0x00),
+            (0x0320, 0x00),
+            (0x0321, 0x01),
+            (0x0322, 0x01),  # N2_UPDATE
+
+            # N3 Configuration (1:1 ratio)
+            (0x0323, 0x00),  # N3_NUM
+            (0x0324, 0x00),
+            (0x0325, 0x00),
+            (0x0326, 0x00),
+            (0x0327, 0x00),
+            (0x0328, 0x01),
+            (0x0329, 0x00),  # N3_DEN
+            (0x032A, 0x00),
+            (0x032B, 0x00),
+            (0x032C, 0x01),
+            (0x032D, 0x01),  # N3_UPDATE
+
+            # Output configuration
+            (0x0112, 0x06),  # OUT0 config
+            (0x0113, 0x09),  # OUT0 format
+            (0x0114, 0x3B),  # OUT0 CM/AMPL
+            (0x0115, 0x28),  # OUT0 MUX_SEL
+
+            (0x0117, 0x06),  # OUT1 config
+            (0x0118, 0x09),  # OUT1 format
+            (0x0119, 0x3B),  # OUT1 CM/AMPL
+            (0x011A, 0x28),  # OUT1 MUX_SEL
+
+            (0x0126, 0x06),  # OUT2 config
+            (0x0127, 0x09),  # OUT2 format
+            (0x0128, 0x3B),  # OUT2 CM/AMPL
+            (0x0129, 0x28),  # OUT2 MUX_SEL
+
+            (0x012B, 0x06),  # OUT3 config
+            (0x012C, 0xCC),  # OUT3 format
+            (0x012D, 0x00),  # OUT3 CM/AMPL
+            (0x012E, 0x58),  # OUT3 MUX_SEL
+
+            # Miscellaneous configuration
+            (0x090E, 0x02),  # XAXB_EXTCLK_EN=0 XAXB_PDNB=1 (use XTAL)
+            (0x091C, 0x04),  # ZDM_EN=4 (Normal mode)
+            (0x0943, 0x00),  # IO_VDD_SEL
+            (0x0949, 0x00),  # IN_EN (disable input clocks)
+            (0x094A, 0x00),  # INx_TO_PFD_EN (disabled)
+            (0x094E, 0x49),  # REFCLK_HYS_SEL (set by CBPro)
+            (0x094F, 0x02),  # Not in datasheet
+            (0x095E, 0x00),  # M_INTEGER (set by CBPro)
+            (0x0A02, 0x00),  # N_ADD_0P5 (set by CBPro)
+            (0x0A03, 0x01),  # N_CLK_TO_OUTX_EN
+            (0x0A04, 0x01),  # N_PIBYP
+            (0x0A05, 0x01),  # N_PDNB
+            (0x0A14, 0x00),  # N0_HIGH_FREQ (set by CBPro)
+            (0x0A1A, 0x00),  # N1_HIGH_FREQ (set by CBPro)
+            (0x0A20, 0x00),  # N2_HIGH_FREQ (set by CBPro)
+            (0x0A26, 0x00),  # N3_HIGH_FREQ (set by CBPro)
+            (0x0B44, 0x0F),  # PDIV_ENB (set by CBPro)
+            (0x0B4A, 0x0E),  # N_CLK_DIS
+            (0x0B57, 0x0E),  # VCO_RESET_CALCODE (set by CBPro)
+            (0x0B58, 0x01),  # VCO_RESET_CALCODE (set by CBPro)
+        ]
+
+        write_preamble(bus)
+
+        time.sleep(0.3)
+
+        print("Writing main configuration...")
+        for address, value in main_config:
+            write_register(bus, address, value)
+        print("Main configuration written")
+
+        write_postamble(bus)
+
+        if not wait_for_lock(bus):
+            print("Error waiting for input clock or PLL lock")
+        else:
+            print("Input clock present and PLL locked")
+
+        bus.write_byte_data(IC_ADDR, STATUS_STICKY, 0)
+
+        # Final status check
+        pll_locked = check_pll_status(bus)
+        xaxb_signal_present = check_los_status(bus)
+
+        if not pll_locked:
+            print("Error: PLL is not locked")
+        elif not xaxb_signal_present:
+            print("Error: XA/XB signal is lost")
+        else:
+            print("Si5340 configuration completed successfully")
+
+if __name__ == "__main__":
+    configure_si5340()

flake.lock

@@ -18,16 +18,16 @@
     },
     "nixpkgs": {
       "locked": {
-        "lastModified": 1706107048,
+        "lastModified": 1723938990,
-        "narHash": "sha256-SqcJ9KxQVY+eLojoqYuJhWa4+D9utUzEuFJzOcUS8iY=",
+        "narHash": "sha256-9tUadhnZQbWIiYVXH8ncfGXGvkNq3Hag4RCBEMUk7MI=",
         "owner": "NixOS",
         "repo": "nixpkgs",
-        "rev": "6fd7935607b68a96949b51ff08f12109e99ffd1f",
+        "rev": "c42fcfbdfeae23e68fc520f9182dde9f38ad1890",
         "type": "github"
       },
       "original": {
         "owner": "NixOS",
-        "ref": "nixos-unstable",
+        "ref": "nixos-24.05",
         "repo": "nixpkgs",
         "type": "github"
       }
@@ -64,11 +64,11 @@
     "src-migen": {
       "flake": false,
       "locked": {
-        "lastModified": 1702942348,
+        "lastModified": 1721561053,
-        "narHash": "sha256-gKIfHZxsv+jcgDFRW9mPqmwqbZXuRvXefkZcSFjOGHw=",
+        "narHash": "sha256-z3LRhNmKZrjr6rFD0yxtccSa/SWvFIYmb+G/D5d2Jd8=",
         "owner": "m-labs",
         "repo": "migen",
-        "rev": "50934ad10a87ade47219b796535978b9bdf24023",
+        "rev": "9279e8623f8433bc4f23ac51e5e2331bfe544417",
         "type": "github"
       },
       "original": {
@@ -80,11 +80,11 @@
     "src-misoc": {
       "flake": false,
       "locked": {
-        "lastModified": 1699352904,
+        "lastModified": 1715647536,
-        "narHash": "sha256-SglyTmXOPv8jJOjwAjJrj/WhAkItQfUbvKfUqrynwRg=",
+        "narHash": "sha256-q+USDcaKHABwW56Jzq8u94iGPWlyLXMyVt0j/Gyg+IE=",
         "ref": "refs/heads/master",
-        "rev": "a53859f2167c31ab5225b6c09f30cf05527b94f4",
+        "rev": "fea9de558c730bc394a5936094ae95bb9d6fa726",
-        "revCount": 2452,
+        "revCount": 2455,
         "submodules": true,
         "type": "git",
         "url": "https://github.com/m-labs/misoc.git"

flake.nix

@@ -1,7 +1,7 @@
 {
   description = "Firmware for Sinara Fast-Servo based on Not-OS and Linien";
   
-  inputs.nixpkgs.url = github:NixOS/nixpkgs/nixos-unstable;
+  inputs.nixpkgs.url = github:NixOS/nixpkgs/nixos-24.05;
   inputs.not-os.url = github:cleverca22/not-os;
   inputs.not-os.inputs.nixpkgs.follows = "nixpkgs";
 
@@ -10,8 +10,8 @@
 
   outputs = { self, nixpkgs, not-os, src-migen, src-misoc }:
     let
-      pkgs = import nixpkgs { system = "x86_64-linux"; };
+      pkgs = import nixpkgs { system = "x86_64-linux"; overlays = [ crosspkgs-overlay ]; };
-      not-os-cfg = not-os-configured.config.system;
+      pkgs-armv7l = pkgs.pkgsCross.zynq-armv7l-linux;
       fsbl-support = ./fast-servo/fsbl-support;
 
       patched-not-os = pkgs.applyPatches {
@@ -23,9 +23,41 @@
           ./not-os-patches/pr-29.patch
           ./not-os-patches/pr-30.patch
           ./not-os-patches/pr-31.patch
+          ./not-os-patches/pr-33.patch
         ];
       };
 
+      crossSystem = {
+        system = "armv7l-linux";
+        linux-kernel = {
+          name = "zynq";
+          baseConfig = "multi_v7_defconfig";
+          target = "uImage";
+          installTarget = "uImage";
+          autoModules = false;
+          DTB = true;
+          makeFlags = [ "LOADADDR=0x8000" ];
+        };
+      };
+
+      crosspkgs-overlay = (self: super: {
+        pkgsCross = super.pkgsCross // {
+          zynq-baremetal = import super.path {
+            system = "x86_64-linux";
+            crossSystem = {
+              config = "arm-none-eabihf";
+              libc = "newlib";
+              gcc.cpu = "cortex-a9";
+              gcc.fpu = "vfpv3";
+            };
+          };
+          zynq-armv7l-linux = import super.path {
+            system = "x86_64-linux";
+            inherit crossSystem;
+          };
+        };
+      });
+
       migen = pkgs.python3Packages.buildPythonPackage rec {
         name = "migen";
         src = src-migen;
@@ -68,127 +100,58 @@
         runScript = "vivado";
       };
 
-      not-os-configured = (import patched-not-os {
+      pyrp3 = pkgs-armv7l.python3Packages.buildPythonPackage rec {
-        inherit nixpkgs;
+        pname = "pyrp3";
-        extraModules = [
+        version = "1.2.0";
-          "${patched-not-os}/zynq_image.nix"
+        pyproject = true;
+        src = pkgs.fetchFromGitHub {
+          owner = "linien-org";
+          repo = "pyrp3";
+          rev = "v${version}";
+          hash = "sha256-43TTlpJ5SMAjQM71bNVvrWQyciRXM3zpuA/Dw41AEgU=";
+        };
+        patches = ./fast-servo/linien-pyrp3-monitor.patch;
+        nativeBuildInputs = with pkgs-armv7l.python3Packages; [
+          setuptools wheel setuptools-scm
+        ] ++ (with pkgs-armv7l; [ gcc gnumake ]);
+        propagatedBuildInputs = with pkgs-armv7l.python3Packages; [
+          myhdl
+          rpyc4
+          cached-property
+          numpy
         ];
-        system = "x86_64-linux";
+        postInstall = ''
-        crossSystem.system = "armv7l-linux";
+          cp monitor/libmonitor.so $out/lib
-      });
+        '';
-
+        postFixup = ''
-      gnu-platform = "arm-none-eabi";
+          substituteInPlace $out/${pkgs.python3.sitePackages}/pyrp3/raw_memory.py \
-
+            --replace "libmonitor.so" "$out/lib/libmonitor.so"
-      binutils-pkg = { zlib, extraConfigureFlags ? [] }: pkgs.stdenv.mkDerivation rec {
-        basename = "binutils";
-        version = "2.30";
-        name = "${basename}-${gnu-platform}-${version}";
-        src = pkgs.fetchurl {
-          url = "https://ftp.gnu.org/gnu/binutils/binutils-${version}.tar.bz2";
-          sha256 = "028cklfqaab24glva1ks2aqa1zxa6w6xmc8q34zs1sb7h22dxspg";
-        };
-        configureFlags = [
-          "--enable-deterministic-archives"
-          "--target=${gnu-platform}"
-          "--with-cpu=cortex-a9"
-          "--with-fpu=vfpv3"
-          "--with-float=hard"
-          "--with-mode=thumb"
-        ] ++ extraConfigureFlags;
-        outputs = [ "out" "info" "man" ];
-        depsBuildBuild = [ pkgs.buildPackages.stdenv.cc ];
-        buildInputs = [ zlib ];
-        enableParallelBuilding = true;
-        meta = {
-          description = "Tools for manipulating binaries (linker, assembler, etc.)";
-          longDescription = ''
-            The GNU Binutils are a collection of binary tools.  The main
-            ones are `ld' (the GNU linker) and `as' (the GNU assembler).
-            They also include the BFD (Binary File Descriptor) library,
-            `gprof', `nm', `strip', etc.
-          '';
-          homepage = http://www.gnu.org/software/binutils/;
-          license = pkgs.lib.licenses.gpl3Plus;
-          /* Give binutils a lower priority than gcc-wrapper to prevent a
-            collision due to the ld/as wrappers/symlinks in the latter. */
-          priority = "10";
-        };
-      };
-
-      gcc-pkg = { gmp, mpfr, libmpc, platform-binutils, extraConfigureFlags ? [] }: pkgs.stdenv.mkDerivation rec {
-        basename = "gcc";
-        version = "9.1.0";
-        name = "${basename}-${gnu-platform}-${version}";
-        src = pkgs.fetchurl {
-          url = "https://ftp.gnu.org/gnu/gcc/gcc-${version}/gcc-${version}.tar.xz";
-          sha256 = "1817nc2bqdc251k0lpc51cimna7v68xjrnvqzvc50q3ax4s6i9kr";
-        };
-        preConfigure = ''
-          mkdir build
-          cd build
         '';
-        configureScript = "../configure";
-        configureFlags = [ 
-          "--target=${gnu-platform}"
-          "--with-arch=armv7-a"
-          "--with-tune=cortex-a9"
-          "--with-fpu=vfpv3"
-          "--with-float=hard"
-          "--disable-libssp"
-          "--enable-languages=c"
-          "--with-as=${platform-binutils}/bin/${gnu-platform}-as"
-          "--with-ld=${platform-binutils}/bin/${gnu-platform}-ld" ] ++ extraConfigureFlags;
-        outputs = [ "out" "info" "man" ];
-        hardeningDisable = [ "format" "pie" ];
-        propagatedBuildInputs = [ gmp mpfr libmpc platform-binutils ];
-        enableParallelBuilding = true;
-        dontFixup = true;
       };
 
-      newlib-pkg = { platform-binutils, platform-gcc }: pkgs.stdenv.mkDerivation rec {
+      linien-server = pkgs-armv7l.python3Packages.buildPythonPackage rec {
-        pname = "newlib";
+        pname = "linien-server";
-        version = "3.1.0";
+        pyproject = true;
-        src = pkgs.fetchurl {
+        inherit (pkgs.python3Packages.linien-common) src version;
-          url = "ftp://sourceware.org/pub/newlib/newlib-${version}.tar.gz";
+        sourceRoot = "source/linien-server";
-          sha256 = "0ahh3n079zjp7d9wynggwrnrs27440aac04340chf1p9476a2kzv";
+        postPatch = ''
-        };
+          cp ${fast-servo-gateware}/csrmap.py linien_server/csrmap.py
-        nativeBuildInputs = [ platform-binutils platform-gcc ];
+          substituteInPlace linien_server/acquisition.py \
-        configureFlags = [
+            --replace "  start_nginx()" "" \
-          "--target=${gnu-platform}"
+            --replace "  stop_nginx()" "" \
-
+            --replace "  flash_fpga()" ""
-          "--with-cpu=cortex-a9"
+        '';
-          "--with-fpu=vfpv3"
+        nativeBuildInputs = [ pkgs-armv7l.python3Packages.setuptools ];
-          "--with-float=hard"
+        propagatedBuildInputs = with pkgs-armv7l.python3Packages; [
-          "--with-mode=thumb"
+          appdirs
-          "--enable-interwork"
+          certifi
-          "--disable-multilib"
+          click
-
+          cma
-          "--disable-newlib-supplied-syscalls"
+          pylpsd
-          "--with-gnu-ld"
+          pyrp3
-          "--with-gnu-as"
+          requests
-          "--disable-newlib-io-float"
+          linien-common
-          "--disable-werror"
         ];
-        dontFixup = true;
-      };
-      
-      gnutoolchain = rec {
-        binutils-bootstrap = pkgs.callPackage binutils-pkg { };
-        gcc-bootstrap = pkgs.callPackage gcc-pkg {
-          platform-binutils = binutils-bootstrap;
-          extraConfigureFlags = [ "--disable-libgcc" ];
-        };
-        newlib = pkgs.callPackage newlib-pkg {
-          platform-binutils = binutils-bootstrap;
-          platform-gcc = gcc-bootstrap;
-        };
-        binutils = pkgs.callPackage binutils-pkg {
-          extraConfigureFlags = [ "--with-lib-path=${newlib}/arm-none-eabi/lib" ];
-        };
-        gcc = pkgs.callPackage gcc-pkg {
-          platform-binutils = binutils;
-          extraConfigureFlags = [ "--enable-newlib" "--with-headers=${newlib}/arm-none-eabi/include" ];
-        };
       };
 
       fast-servo-gateware = pkgs.stdenv.mkDerivation rec {
@@ -223,11 +186,33 @@
           mkdir -p $out $out/nix-support
           cp gateware/build/top.bit $out
           cp linien-server/linien_server/gateware.bin $out
+          cp linien-server/linien_server/csrmap.py $out
           echo file binary-dist $out/top.bit >> $out/nix-support/hydra-build-products
           echo file binary-dist $out/gateware.bin >> $out/nix-support/hydra-build-products
         '';
       };
 
+      pyfastservo = pkgs-armv7l.python3Packages.buildPythonPackage rec {
+        name = "pyfastservo";
+        src = ./fast-servo;
+        preBuild = ''
+          cat > setup.py << EOF
+          from setuptools import setup
+
+          setup(
+            name="pyfastservo",
+            packages=["pyfastservo"],
+            install_requires=["spidev", "smbus2"],
+            entry_points = {"console_scripts": ["fp_leds=pyfastservo.fp_leds:main"]},
+          )
+          EOF
+        '';
+        propagatedBuildInputs = with pkgs-armv7l.python3Packages; [
+          spidev
+          smbus2
+        ];
+      };
+
       mkbootimage = pkgs.stdenv.mkDerivation {
         pname = "mkbootimage";
         version = "2.3dev";
@@ -251,16 +236,38 @@
         hardeningDisable = [ "fortify" ];
       };
 
-      # Pinned qemu version due to networking errors in recent version 8.2.0
-      qemu = pkgs.qemu.overrideAttrs (oldAttrs: rec {
-        version = "8.1.3";
-        src = pkgs.fetchurl {
-          url = "https://download.qemu.org/qemu-${version}.tar.xz";
-          hash = "sha256-Q8wXaAQQVYb3T5A5jzTp+FeH3/QA07ZA2B93efviZbs=";
-        };
-      });
-
       board-package-set = { board }: let
+        not-os-configured = (import patched-not-os {
+          inherit nixpkgs;
+          extraModules = [
+            "${patched-not-os}/zynq_image.nix"
+          ] ++ pkgs.lib.optionals (board == "fast-servo") [
+            ({ config, pkgs, lib, ... }: {
+              environment.systemPackages = [
+                linien-server
+                (pkgs.python3.withPackages(ps: [ pyfastservo ]))
+              ];
+              boot.postBootCommands = lib.mkAfter ''
+
+                # Program the FPGA
+                set +x
+                echo "Loading bitstream into SRAM..."
+                echo 0 > /sys/class/fpga_manager/fpga0/flags
+                mkdir -p /lib/firmware
+                cp ${fast-servo-gateware}/gateware.bin /lib/firmware/
+                echo gateware.bin > /sys/class/fpga_manager/fpga0/firmware
+
+                # Run device init scripts
+                echo "Initializing clock generator, ADC, and DAC..."
+                python3 -m pyfastservo.initialize
+              '';
+            })];
+          system = "x86_64-linux";
+          inherit crossSystem;
+        });
+
+        not-os-build = not-os-configured.config.system.build;
+
         fsbl = pkgs.stdenv.mkDerivation {
           name = "${board}-fsbl";
           src = pkgs.fetchFromGitHub {
@@ -270,9 +277,8 @@
             sha256 = "sha256-UDz9KK/Hw3qM1BAeKif30rE8Bi6C2uvuZlvyvtJCMfw=";
           };
           nativeBuildInputs = [
-            pkgs.gnumake
+            pkgs.pkgsCross.zynq-baremetal.buildPackages.binutils
-            gnutoolchain.binutils
+            pkgs.pkgsCross.zynq-baremetal.buildPackages.gcc
-            gnutoolchain.gcc
           ];
           postUnpack = ''
             mkdir -p $sourceRoot/lib/sw_apps/zynq_fsbl/misc/fast-servo
@@ -282,7 +288,11 @@
           patches = [] ++ pkgs.lib.optional (board == "fast-servo") ./fast-servo/fsbl.patch;
           postPatch = ''
             patchShebangs lib/sw_apps/zynq_fsbl/misc/copy_bsp.sh
-            echo 'SEARCH_DIR("${gnutoolchain.newlib}/arm-none-eabi/lib");' >> lib/sw_apps/zynq_fsbl/src/lscript.ld
+
+            for x in lib/sw_apps/zynq_fsbl/src/Makefile lib/sw_apps/zynq_fsbl/misc/copy_bsp.sh lib/bsp/standalone/src/arm/cortexa9/gcc/Makefile; do
+              substituteInPlace $x \
+                --replace "arm-none-eabi-" "arm-none-eabihf-"
+            done
           '';
           buildPhase = ''
             cd lib/sw_apps/zynq_fsbl/src
@@ -296,9 +306,8 @@
           dontFixup = true;
         };
 
-        u-boot = let
+        u-boot = (pkgs-armv7l.buildUBoot {
-          fast-servo-dts = fast-servo/fast-servo.dts;
+            name = "${board}-u-boot";
-          in (pkgs.pkgsCross.armv7l-hf-multiplatform.buildUBoot {
             defconfig = "xilinx_zynq_virt_defconfig";
             patches = [] ++ pkgs.lib.optional (board == "fast-servo") ./fast-servo/u-boot.patch;
             preConfigure = ''
@@ -308,7 +317,7 @@
               CONFIG_SYS_PROMPT="${board}-boot> "
               CONFIG_AUTOBOOT=y
               CONFIG_BOOTCOMMAND="${builtins.replaceStrings [ "\n" ] [ "; " ] ''
-                setenv bootargs 'root=/dev/mmcblk0p2 console=ttyPS0,115200n8 systemConfig=${builtins.unsafeDiscardStringContext not-os-cfg.build.toplevel}'
+                setenv bootargs 'root=/dev/mmcblk0p2 console=ttyPS0,115200n8 systemConfig=${builtins.unsafeDiscardStringContext not-os-build.toplevel}'
                 fatload mmc 0 0x6400000 uImage
                 fatload mmc 0 0x8000000 ${board}.dtb
                 fatload mmc 0 0xA400000 uRamdisk.image.gz
@@ -321,7 +330,7 @@
             filesToInstall = [ "u-boot.elf" ];
           }).overrideAttrs (oldAttrs: {
             postUnpack = ''
-              cp ${fast-servo-dts} $sourceRoot/arch/arm/dts/zynq-fast-servo.dts
+              cp ${fast-servo/fast-servo.dts} $sourceRoot/arch/arm/dts/zynq-fast-servo.dts
             '';
             postInstall = ''
               mkdir -p $out/dts
@@ -352,7 +361,7 @@
             echo file binary-dist $out/boot.bin >> $out/nix-support/hydra-build-products
           '';
 
-        dtb = pkgs.runCommand "dtb"
+        dtb = pkgs.runCommand "${board}-dtb"
           {
             buildInputs = [ pkgs.gcc pkgs.dtc ];
           }
@@ -372,14 +381,14 @@
 
         sd-image = let
           rootfsImage = pkgs.callPackage (pkgs.path + "/nixos/lib/make-ext4-fs.nix") {
-            storePaths = [ not-os-cfg.build.toplevel ];
+            storePaths = [ not-os-build.toplevel ];
             volumeLabel = "ROOT";
           };
           # Current firmware (kernel, bootimage, etc..) takes ~18MB
           firmwareSize = 30;
           firmwarePartitionOffset = 8;
           in pkgs.stdenv.mkDerivation {
-            name = "sd-image";
+            name = "${board}-sd-image";
             nativeBuildInputs = with pkgs; [ dosfstools mtools libfaketime util-linux parted ];
             buildCommand = ''
               mkdir -p $out/nix-support $out/sd-image
@@ -413,8 +422,8 @@
               mkdir firmware
               cp ${bootimage}/boot.bin firmware/
               cp ${dtb}/${board}.dtb firmware/
-              cp ${not-os-cfg.build.kernel}/uImage firmware/
+              cp ${not-os-build.kernel}/uImage firmware/
-              cp ${not-os-cfg.build.uRamdisk}/initrd firmware/uRamdisk.image.gz
+              cp ${not-os-build.uRamdisk}/initrd firmware/uRamdisk.image.gz
 
               (cd firmware; mcopy -psvm -i ../firmware_part.img ./* ::)
               dd conv=notrunc if=firmware_part.img of=$img seek=$START count=$SECTORS
@@ -424,10 +433,12 @@
         not-os-qemu = let
           qemuScript = ''
             #!/bin/bash
-            export PATH=${qemu}/bin:$PATH
+            export PATH=${pkgs.qemu}/bin:$PATH
             IMGDIR=$(mktemp -d /tmp/not-os-qemu-XXXXXX)
             BASE=$(realpath $(dirname $0))
-            qemu-img create -F raw -f qcow2 -b $BASE/sd-image.img $IMGDIR/sd-overlay.qcow2 512M
+
+            qemu-img convert -O qcow2 -f raw -o preallocation=metadata $BASE/sd-image.img $IMGDIR/sd-sparse.qcow2
+            qemu-img create -F qcow2 -f qcow2 -b $IMGDIR/sd-sparse.qcow2 $IMGDIR/sd-overlay.qcow2 2G
 
             # Some command arguments are based from samples in Xilinx QEMU User Documentation
             # See: https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/821854273/Running+Bare+Metal+Applications+on+QEMU
@@ -442,7 +453,7 @@
 
             rm -rf $IMGDIR
           '';
-          in pkgs.runCommand "not-os-qemu" {
+          in pkgs.runCommand "${board}-qemu" {
             inherit qemuScript;
             passAsFile = [ "qemuScript" ];
             preferLocalBuild = true;
@@ -470,11 +481,10 @@
         inherit migen misoc vivado;
       };
       packages.armv7l-linux = {
-        inherit fast-servo-gateware;
+        inherit fast-servo-gateware linien-server;
       } //
       (board-package-set { board = "zc706"; }) //
       (board-package-set { board = "fast-servo"; });
-
       hydraJobs = packages.x86_64-linux // packages.armv7l-linux;
     };
 

not-os-patches/network.patch

@@ -1,5 +1,5 @@
 diff --git a/configuration.nix b/configuration.nix
-index 010c487..e1e85ba 100644
+index 010c487..2d08009 100644
 --- a/configuration.nix
 +++ b/configuration.nix
 @@ -1,4 +1,4 @@
@@ -8,7 +8,7 @@ index 010c487..e1e85ba 100644
  
  {
    imports = [ ./qemu.nix ];
-@@ -7,10 +7,15 @@
+@@ -7,10 +7,16 @@
    environment.etc = {
      "ssh/authorized_keys.d/root" = {
        text = ''
@@ -18,6 +18,7 @@ index 010c487..e1e85ba 100644
 +        ecdsa-sha2-nistp384 AAAAE2VjZHNhLXNoYTItbmlzdHAzODQAAAAIbmlzdHAzODQAAABhBNdIiLvP2hmDUFyyE0oLOIXrjrMdWWpBV9/gPR5m4AiARx4JkufIDZzmptdYQ5FhJORJ4lluPqp7dAmahoSwg4lv9Di0iNQpHMJvNGZLHYKM1H1FWCCFIEDJ8bD4SVfrDg== root
 +        ecdsa-sha2-nistp384 AAAAE2VjZHNhLXNoYTItbmlzdHAzODQAAAAIbmlzdHAzODQAAABhBF/YybP+fQ0J+bNqM5Vgx5vDmVqVWsgUdF1moUxghv7d73GZAFaM6IFBdrXTAa33AwnWwDPMrTgP1V6SXBkb3ciJo/lD1urJGbydbSI5Ksq9d59wvOeANvyWYrQw6+eqTQ== sb
 +        ecdsa-sha2-nistp384 AAAAE2VjZHNhLXNoYTItbmlzdHAzODQAAAAIbmlzdHAzODQAAABhBFkmOCQ3BQh3qUjLtfdqyeBsx8rkk/QYlzB0TMrnfn6waLN6yKfPC3WVFv4zN5kNKb/OayvqDa+zfkKe85e/oIPQQKflF7GrCHdssz33DCnW90cz532E6iqG1pjeZjID2A== flo
++        ssh-ed25519 AAAAC3NzaC1lZDI1NTE5AAAAICAranL376soiSJ0kxdYNrwElcaZPW1heLFjs8Y7n0jT linuswck
        '';
        mode = "0444";
      };

not-os-patches/pr-28.patch

@@ -1,5 +1,5 @@
 diff --git a/base.nix b/base.nix
-index 7eaee32..3a2a0a9 100644
+index 7eaee32..9aa338e 100644
 --- a/base.nix
 +++ b/base.nix
 @@ -27,6 +27,11 @@ with lib;
@@ -14,9 +14,12 @@ index 7eaee32..3a2a0a9 100644
      not-os.simpleStaticIp = mkOption {
        type = types.bool;
        default = false;
-@@ -86,15 +91,25 @@ with lib;
+@@ -84,17 +89,25 @@ with lib;
+     };
+     environment.etc = {
        "nix/nix.conf".source = pkgs.runCommand "nix.conf" {} ''
-         extraPaths=$(for i in $(cat ${pkgs.writeReferencesToFile pkgs.runtimeShell}); do if test -d $i; then echo $i; fi; done)
+-        extraPaths=$(for i in $(cat ${pkgs.writeReferencesToFile pkgs.runtimeShell}); do if test -d $i; then echo $i; fi; done)
++        extraPaths=$(for i in $(cat ${pkgs.writeClosure [ pkgs.bash ]}); do if test -d $i; then echo $i; fi; done)
          cat > $out << EOF
 -        build-use-sandbox = true
 +        auto-optimise-store = true
@@ -28,8 +31,6 @@ index 7eaee32..3a2a0a9 100644
 +        extra-sandbox-paths = /bin/sh=${pkgs.runtimeShell} $(echo $extraPaths)
 +        max-jobs = auto
 +        sandbox = true
-+        substituters = https://cache.armv7l.xyz
-+        trusted-public-keys = cache.armv7l.xyz-1:kBY/eGnBAYiqYfg0fy0inWhshUo+pGFM3Pj7kIkmlBk=
 +        trusted-users = root
          EOF
        '';
@@ -151,10 +152,10 @@ index c61f9d6..fbdf0fd 100644
    };
  }
 diff --git a/zynq_image.nix b/zynq_image.nix
-index 3fa23ab..727e3ef 100644
+index 3fa23ab..069fe89 100644
 --- a/zynq_image.nix
 +++ b/zynq_image.nix
-@@ -1,66 +1,96 @@
+@@ -1,66 +1,89 @@
 -{ config, pkgs, ... }:
 +{ lib, config, pkgs, ... }:
  
@@ -163,22 +164,7 @@ index 3fa23ab..727e3ef 100644
 -  # dont use overlays for the qemu, it causes a lot of wasted time on recompiles
 -  x86pkgs = import pkgs.path { system = "x86_64-linux"; };
 -  customKernel = pkgs.linux.override {
-+  crosspkgs = import pkgs.path {
++  customKernel = (pkgs.linux_6_6.override {
-+    system = "x86_64-linux";
-+    crossSystem = {
-+      system = "armv7l-linux";
-+      linux-kernel = {
-+        name = "zynq";
-+        baseConfig = "multi_v7_defconfig";
-+        target = "uImage";
-+        installTarget = "uImage";
-+        autoModules = false;
-+        DTB = true;
-+        makeFlags = [ "LOADADDR=0x8000" ];
-+      };
-+    };
-+  };
-+  customKernel = (crosspkgs.linux.override {
      extraConfig = ''
        OVERLAY_FS y
 +      MEDIA_SUPPORT n
@@ -187,16 +173,23 @@ index 3fa23ab..727e3ef 100644
 +      SOUND n
 +      SQUASHFS n
 +      BACKLIGHT_CLASS_DEVICE n
++      FPGA y
++      FPGA_BRIDGE y
++      FPGA_REGION y
++      OF_FPGA_REGION y
++      FPGA_MGR_ZYNQ_FPGA y
++      OF_OVERLAY y
      '';
 -  };
--  customKernelPackages = pkgs.linuxPackagesFor customKernel;
 +  }).overrideAttrs (oa: {
 +    postInstall = ''
-+      cp arch/arm/boot/uImage $out
++      if [ -e arch/arm/boot/uImage ]; then
++        cp arch/arm/boot/uImage $out
++      fi
 +      ${oa.postInstall}
 +    '';
 +  });
-+  customKernelPackages = crosspkgs.linuxPackagesFor customKernel;
+   customKernelPackages = pkgs.linuxPackagesFor customKernel;
  in {
    imports = [ ./arm32-cross-fixes.nix ];
    boot.kernelPackages = customKernelPackages;
@@ -247,17 +240,17 @@ index 3fa23ab..727e3ef 100644
 -    chmod +x qemu-script
 -    patchShebangs qemu-script
 -    ls -ltrh
-   '';
+-  '';
 -  system.build.rpi_image_tar = pkgs.runCommand "dist.tar" {} ''
 -    mkdir -p $out/nix-support
 -    tar -cvf $out/dist.tar ${config.system.build.rpi_image}
 -    echo "file binary-dist $out/dist.tar" >> $out/nix-support/hydra-build-products
--  '';
+   '';
 -  environment.systemPackages = [ pkgs.strace ];
 -  environment.etc."service/getty/run".source = pkgs.writeShellScript "getty" ''
 -    agetty ttyPS0 115200
 +  environment = {
-+    systemPackages = with pkgs; [ inetutils wget nano ];
++    systemPackages = with pkgs; [ inetutils wget gnugrep nano vim ];
 +    etc = {
 +      "service/getty/run".source = pkgs.writeShellScript "getty" ''
 +        hostname ${config.networking.hostName}