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@ -394,10 +394,10 @@ index 0000000..53c5349
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\ No newline at end of file
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diff --git a/xilinx-fpga-manager.patch b/xilinx-fpga-manager.patch
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new file mode 100644
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index 0000000..59aa585
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index 0000000..33daffe
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--- /dev/null
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+++ b/xilinx-fpga-manager.patch
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@@ -0,0 +1,663 @@
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@@ -0,0 +1,676 @@
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+# Enable user-space interface for PL programming via Linux FPGA manager
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+# diff cherry-picked from Xilinx/linux-xilinx/tree/xlnx_rebase_v6.6_LTS
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+# commit IDs: e61c0a9, 0a38712, dc67651, 89a24e3, 8d224b1, 2a9c05f, 4e94580
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@ -425,7 +425,7 @@ index 0000000..59aa585
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+ tristate "Altera SOCFPGA FPGA Manager"
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+ depends on ARCH_INTEL_SOCFPGA || COMPILE_TEST
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+diff --git a/drivers/fpga/fpga-mgr.c b/drivers/fpga/fpga-mgr.c
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+index 06651389c592..6e8c45974f28 100644
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+index 0f4035b089a2..3aa9f5f041f6 100644
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+--- a/drivers/fpga/fpga-mgr.c
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++++ b/drivers/fpga/fpga-mgr.c
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+@@ -8,6 +8,9 @@
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@ -673,7 +673,7 @@ index 0000000..59aa585
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+ NULL,
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+ };
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+ ATTRIBUTE_GROUPS(fpga_mgr);
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+@@ -732,6 +864,106 @@ void fpga_mgr_put(struct fpga_manager *mgr)
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+@@ -739,6 +871,106 @@ void fpga_mgr_put(struct fpga_manager *mgr)
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+ }
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+ EXPORT_SYMBOL_GPL(fpga_mgr_put);
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+
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@ -780,8 +780,8 @@ index 0000000..59aa585
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+ /**
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+ * fpga_mgr_lock - Lock FPGA manager for exclusive use
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+ * @mgr: fpga manager
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+@@ -779,6 +1011,9 @@ struct fpga_manager *
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+ fpga_mgr_register_full(struct device *parent, const struct fpga_manager_info *info)
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+@@ -788,6 +1020,9 @@ __fpga_mgr_register_full(struct device *parent, const struct fpga_manager_info *
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+ struct module *owner)
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+ {
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+ const struct fpga_manager_ops *mops = info->mops;
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++#ifdef CONFIG_FPGA_MGR_DEBUG_FS
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@ -790,7 +790,7 @@ index 0000000..59aa585
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+ struct fpga_manager *mgr;
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+ int id, ret;
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+
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+@@ -815,10 +1050,28 @@ fpga_mgr_register_full(struct device *parent, const struct fpga_manager_info *in
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+@@ -826,10 +1061,28 @@ __fpga_mgr_register_full(struct device *parent, const struct fpga_manager_info *
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+ mgr->dev.of_node = parent->of_node;
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+ mgr->dev.id = id;
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+
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@ -819,7 +819,7 @@ index 0000000..59aa585
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+ /*
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+ * Initialize framework state by requesting low level driver read state
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+ * from device. FPGA may be in reset mode or may have been programmed
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+@@ -832,6 +1085,28 @@ fpga_mgr_register_full(struct device *parent, const struct fpga_manager_info *in
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+@@ -843,6 +1096,28 @@ __fpga_mgr_register_full(struct device *parent, const struct fpga_manager_info *
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+ return ERR_PTR(ret);
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+ }
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+
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@ -848,7 +848,7 @@ index 0000000..59aa585
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+ return mgr;
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+
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+ error_device:
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+@@ -882,6 +1157,10 @@ void fpga_mgr_unregister(struct fpga_manager *mgr)
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+@@ -894,6 +1169,10 @@ void fpga_mgr_unregister(struct fpga_manager *mgr)
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+ {
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+ dev_info(&mgr->dev, "%s %s\n", __func__, mgr->name);
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+
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@ -881,10 +881,10 @@ index 0000000..59aa585
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+ &firmware_name)) {
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+ info->firmware_name = devm_kstrdup(dev, firmware_name,
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+diff --git a/drivers/fpga/zynqmp-fpga.c b/drivers/fpga/zynqmp-fpga.c
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+index f3434e2c487b..db923746cac5 100644
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+index f3434e2c487b..d2434ed85eff 100644
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+--- a/drivers/fpga/zynqmp-fpga.c
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++++ b/drivers/fpga/zynqmp-fpga.c
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+@@ -43,25 +43,42 @@ static int zynqmp_fpga_ops_write(struct fpga_manager *mgr,
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+@@ -43,25 +43,47 @@ static int zynqmp_fpga_ops_write(struct fpga_manager *mgr,
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+ struct zynqmp_fpga_priv *priv;
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+ dma_addr_t dma_addr;
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+ u32 eemi_flags = 0;
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@ -915,6 +915,11 @@ index 0000000..59aa585
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++
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+ wmb(); /* ensure all writes are done before initiate FW call */
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+
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++ if (priv->flags & FPGA_MGR_DDR_MEM_AUTH_BITSTREAM)
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++ eemi_flags |= XILINX_ZYNQMP_PM_FPGA_AUTHENTICATION_DDR;
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++ else if (priv->flags & FPGA_MGR_SECURE_MEM_AUTH_BITSTREAM)
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++ eemi_flags |= XILINX_ZYNQMP_PM_FPGA_AUTHENTICATION_OCM;
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++
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+ if (priv->flags & FPGA_MGR_PARTIAL_RECONFIG)
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+ eemi_flags |= XILINX_ZYNQMP_PM_FPGA_PARTIAL;
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+
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@ -931,20 +936,22 @@ index 0000000..59aa585
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+ return ret;
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+ }
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+diff --git a/include/linux/firmware/xlnx-zynqmp.h b/include/linux/firmware/xlnx-zynqmp.h
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+index 9dda7d9898ff..edaf77160746 100644
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+index e8b12ec8b060..ffd2dfdb6abd 100644
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+--- a/include/linux/firmware/xlnx-zynqmp.h
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++++ b/include/linux/firmware/xlnx-zynqmp.h
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+@@ -70,6 +70,8 @@
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+@@ -83,6 +83,10 @@
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+ */
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+ #define XILINX_ZYNQMP_PM_FPGA_FULL 0x0U
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+ #define XILINX_ZYNQMP_PM_FPGA_PARTIAL BIT(0)
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++#define XILINX_ZYNQMP_PM_FPGA_AUTHENTICATION_DDR BIT(1)
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++#define XILINX_ZYNQMP_PM_FPGA_AUTHENTICATION_OCM BIT(2)
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++#define XILINX_ZYNQMP_PM_FPGA_ENCRYPTION_USERKEY BIT(3)
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++#define XILINX_ZYNQMP_PM_FPGA_ENCRYPTION_DEVKEY BIT(4)
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+
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+ /* FPGA Status Reg */
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+ #define XILINX_ZYNQMP_PM_FPGA_CONFIG_STAT_OFFSET 7U
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+diff --git a/include/linux/fpga/fpga-mgr.h b/include/linux/fpga/fpga-mgr.h
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+index 54f63459efd6..c96a4405f909 100644
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+index 0d4fe068f3d8..f884d268c974 100644
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+--- a/include/linux/fpga/fpga-mgr.h
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++++ b/include/linux/fpga/fpga-mgr.h
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+@@ -9,8 +9,11 @@
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@ -959,7 +966,7 @@ index 0000000..59aa585
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+ struct fpga_manager;
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+ struct sg_table;
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+
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+@@ -66,17 +69,25 @@ enum fpga_mgr_states {
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+@@ -66,17 +69,29 @@ enum fpga_mgr_states {
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+ *
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+ * %FPGA_MGR_EXTERNAL_CONFIG: FPGA has been configured prior to Linux booting
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+ *
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@ -973,6 +980,10 @@ index 0000000..59aa585
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++ *
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++ * %FPGA_MGR_USERKEY_ENCRYPTED_BITSTREAM: indicates bitstream is encrypted with
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++ * user key
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++ * %FPGA_MGR_DDR_MEM_AUTH_BITSTREAM: do bitstream authentication using DDR
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++ * memory if supported
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++ * %FPGA_MGR_SECURE_MEM_AUTH_BITSTREAM: do bitstream authentication using secure
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++ * memory if supported
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+ */
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+ #define FPGA_MGR_PARTIAL_RECONFIG BIT(0)
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+ #define FPGA_MGR_EXTERNAL_CONFIG BIT(1)
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@ -986,7 +997,7 @@ index 0000000..59aa585
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+
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+ /**
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+ * struct fpga_image_info - information specific to an FPGA image
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+@@ -86,6 +97,7 @@ enum fpga_mgr_states {
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+@@ -86,6 +101,7 @@ enum fpga_mgr_states {
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+ * @config_complete_timeout_us: maximum time for FPGA to switch to operating
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+ * status in the write_complete op.
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+ * @firmware_name: name of FPGA image firmware file
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@ -994,7 +1005,7 @@ index 0000000..59aa585
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+ * @sgt: scatter/gather table containing FPGA image
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+ * @buf: contiguous buffer containing FPGA image
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+ * @count: size of buf
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+@@ -102,6 +114,7 @@ struct fpga_image_info {
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+@@ -102,6 +118,7 @@ struct fpga_image_info {
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+ u32 disable_timeout_us;
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|
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+ u32 config_complete_timeout_us;
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|
|
+ char *firmware_name;
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@ -1002,7 +1013,7 @@ index 0000000..59aa585
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+ struct sg_table *sgt;
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+ const char *buf;
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+ size_t count;
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+@@ -160,6 +173,7 @@ struct fpga_manager_info {
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+@@ -160,6 +177,7 @@ struct fpga_manager_info {
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+ * @write: write count bytes of configuration data to the FPGA
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+ * @write_sg: write the scatter list of configuration data to the FPGA
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+ * @write_complete: set FPGA to operating state after writing is done
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@ -1010,7 +1021,7 @@ index 0000000..59aa585
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+ * @fpga_remove: optional: Set FPGA into a specific state during driver remove
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+ * @groups: optional attribute groups.
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+ *
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+@@ -182,6 +196,7 @@ struct fpga_manager_ops {
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+@@ -182,6 +200,7 @@ struct fpga_manager_ops {
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+ int (*write_sg)(struct fpga_manager *mgr, struct sg_table *sgt);
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+ int (*write_complete)(struct fpga_manager *mgr,
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+ struct fpga_image_info *info);
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@ -1018,7 +1029,7 @@ index 0000000..59aa585
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+ void (*fpga_remove)(struct fpga_manager *mgr);
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+ const struct attribute_group **groups;
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+ };
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+@@ -196,21 +211,35 @@ struct fpga_manager_ops {
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+@@ -196,23 +215,37 @@ struct fpga_manager_ops {
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+ /**
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+ * struct fpga_manager - fpga manager structure
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+ * @name: name of low level fpga manager
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@ -1031,6 +1042,7 @@ index 0000000..59aa585
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+ * @state: state of fpga manager
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+ * @compat_id: FPGA manager id for compatibility check.
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+ * @mops: pointer to struct of fpga manager ops
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+ * @mops_owner: module containing the mops
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+ * @priv: low level driver private date
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++ * @err: low level driver error code
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++ * @dir: debugfs image directory
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@ -1046,6 +1058,7 @@ index 0000000..59aa585
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+ enum fpga_mgr_states state;
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+ struct fpga_compat_id *compat_id;
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+ const struct fpga_manager_ops *mops;
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+ struct module *mops_owner;
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+ void *priv;
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++ int err;
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++#ifdef CONFIG_FPGA_MGR_DEBUG_FS
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@ -1054,21 +1067,21 @@ index 0000000..59aa585
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+ };
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+
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+ #define to_fpga_manager(d) container_of(d, struct fpga_manager, dev)
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+@@ -244,4 +273,6 @@ struct fpga_manager *
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+ devm_fpga_mgr_register(struct device *parent, const char *name,
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+ const struct fpga_manager_ops *mops, void *priv);
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+@@ -258,4 +291,6 @@ __devm_fpga_mgr_register(struct device *parent, const char *name,
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+ const struct fpga_manager_ops *mops, void *priv,
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+ struct module *owner);
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+
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|
++#define FPGA_IOCTL_LOAD_DMA_BUFF _IOWR('R', 1, __u32)
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++
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+ #endif /*_LINUX_FPGA_MGR_H */
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diff --git a/zynq_image.nix b/zynq_image.nix
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index 9d1621e..012e50c 100644
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index d5c5eda..7ede584 100644
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--- a/zynq_image.nix
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|
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|
+++ b/zynq_image.nix
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|
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|
@@ -3,6 +3,16 @@
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|
|
with lib;
|
|
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|
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let
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|
customKernel = (pkgs.linux.override {
|
|
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|
|
customKernel = (pkgs.linux_6_6.override {
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|
|
+ kernelPatches = [
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+ ({
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|
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+ name = "xilinx-configfs-overlays";
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|