diff --git a/fast-servo/pyfastservo/adc.py b/fast-servo/pyfastservo/adc.py
index 900b407..e04a47e 100644
--- a/fast-servo/pyfastservo/adc.py
+++ b/fast-servo/pyfastservo/adc.py
@@ -17,6 +17,8 @@
# You should have received a copy of the GNU General Public License
# along with this program. If not, see .
+import mmap
+import os
import spidev
from pyfastservo.common import (
@@ -31,8 +33,6 @@ from pyfastservo.common import (
AUX_ADC_ADDR,
MAP_MASK,
PAGESIZE,
- write_to_memory,
- read_from_memory
)
# /dev/spidev1.0 <=> spidev.
@@ -44,120 +44,276 @@ AUX_ADC_PORT_A = 2
AUX_ADC_PORT_B = 3
-def spi_write(spi, address, value):
- spi.xfer2([address, value])
-
-def spi_read(spi, address):
- rx_buffer = spi.xfer2([0x80 | address, 0x00])
- return rx_buffer[1]
-
-def main_adc_config(spi, test_pattern):
+def main_adc_config(test_pattern):
high_word = (test_pattern & 0xFF00) >> 8
low_word = test_pattern & 0xFF
- spi_write(spi, 0x00, 0x80) # reset
- spi_write(spi, 0x01, 0x20) # REGISTER A1: set to Two's complement Data Format
- spi_write(spi, 0x02, 0x15) # REGISTER A2: set to LVDS output, set 4 data lanes and turn on test mode
- spi_write(spi, 0x03, high_word) # REGISTER A3: test pattern high word
- spi_write(spi, 0x04, low_word) # REGISTER A4: test pattern low word
-
-def main_adc_test_mode(spi, enable):
- reg_contents = 0x15 if enable else 0x11 # set to LVDS output, set 4 data lanes and turn on or off test mode
- spi_write(spi, 0x02, reg_contents)
-
-def verify_adc_registers(spi, reg_to_check):
- for register, expected_value in reg_to_check.items():
- value = spi_read(spi, register)
- print(f"Spi readback register 0x{register:02x}: 0x{value:02x}")
- if value != expected_value:
- print(f"Different value read than sent in reg 0x{register:02x}")
-
-def read_frame():
- return read_from_memory(ADC_FRAME_ADDR, 1)[0]
-
-def perform_bitslip():
- for i in range(4):
- current_frame = read_frame()
- if current_frame != 0x0C:
- print(f"Performing bitslip (iteration: {i}). Current frame: 0x{current_frame:02x}")
- write_to_memory(ADC_BITSLIP_ADDR, 1)
- else:
- print(f"No bitslip required; Current frame: 0x{current_frame:02x}")
- return
-
-def find_edge():
- prev_frame = read_frame()
- transition = False
- for tap_delay in range(32):
- write_to_memory(ADC_DELAY_ADDR, tap_delay)
- current_frame = read_frame()
-
- print(f"Tap delay: {tap_delay}, Current frame: 0x{current_frame:02x}")
-
- if current_frame != prev_frame:
- if not transition:
- transition = True
- else:
- final_delay = (tap_delay // 2) + 2
- print(f"Edge detected; setting iDelay to: {final_delay}")
- write_to_memory(ADC_DELAY_ADDR, final_delay)
- return
-
- prev_frame = current_frame
-
- # If no edge detected
- final_delay = 11
- print(f"No edge detected; setting iDelay to: {final_delay}")
- write_to_memory(ADC_DELAY_ADDR, final_delay)
-
-def read_adc_channel(high_addr, low_addr):
- return (read_from_memory(high_addr, 1)[0] << 8) | read_from_memory(low_addr, 1)[0]
-
-def print_adc_channels():
- adc_ch0 = read_adc_channel(ADC_CH0_HIGH_ADDR, ADC_CH0_LOW_ADDR)
- adc_ch1 = read_adc_channel(ADC_CH1_HIGH_ADDR, ADC_CH1_LOW_ADDR)
- print(f"Final ADC_CH0: 0x{adc_ch0:04x}")
- print(f"Final ADC_CH1: 0x{adc_ch1:04x}")
-
-def enable_adc_afe(ch1_x10=False, ch2_x10=False):
- ctrl_value = (ch2_x10 << 1) | ch1_x10
- write_to_memory(ADC_AFE_CTRL_ADDR, ctrl_value)
- afe_ctrl = read_from_memory(ADC_AFE_CTRL_ADDR, 1)[0]
- print(f"ADC_AFE_CTRL: 0x{afe_ctrl:02X}")
- return afe_ctrl
-
-def configure_ltc2195():
spi = spidev.SpiDev()
+
try:
spi.open(MAIN_ADC_BUS, MAIN_ADC_DEVICE)
spi.max_speed_hz = 50000
spi.mode = 0b00 # CPOL = 0 CPHA = 0
spi.cshigh = False
+ # spi.read0 = False
- test_pattern = 0x811F
- main_adc_config(spi, test_pattern)
+ spi_buffer = [0x00, 0x80] # reset
+ rx_buffer = [0x00, 0x00]
- verify_adc_registers(spi, {
- 0x01: 0x20,
- 0x02: 0x15,
- 0x03: (test_pattern & 0xFF00) >> 8,
- 0x04: test_pattern & 0xFF
- })
+ spi.xfer2(spi_buffer)
- # Performing Word Align
- perform_bitslip()
- find_edge()
- print_adc_channels()
+ # REGISTER A1
+ spi_buffer = [0x01, 0x20] # set to Two's complement Data Format
+ spi.xfer2(spi_buffer)
- main_adc_test_mode(spi, False)
- verify_adc_registers(spi, {0x02: 0x11}) # Verify test mode is off
-
- print_adc_channels()
+ # read values back
+ spi_buffer = [0x81, 0x00]
+ rx_buffer = spi.xfer2(spi_buffer)
+ print(f"Spi readback register 0x01: 0x{rx_buffer[1]:02x}")
+ if rx_buffer[1] != 0x20:
+ print("Different value read than sent in reg 0x02")
- enable_adc_afe()
+ # REGISTER A2
+ spi_buffer = [
+ 0x02,
+ 0x15,
+ ] # set to LVDS output, set 4 data lanes and turn on test mode
+ spi.xfer2(spi_buffer)
+
+ # read values back
+ spi_buffer = [0x82, 0x00]
+ rx_buffer = spi.xfer2(spi_buffer)
+ print(f"Spi readback register 0x02: 0x{rx_buffer[1]:02x}")
+ if rx_buffer[1] != 0x15:
+ print("Different value read than sent in reg 0x02")
+
+ # REGISTER A3
+ # test pattern high word
+ spi_buffer = [0x03, high_word]
+ spi.xfer2(spi_buffer)
+
+ # read balues back
+ spi_buffer = [0x83, 0x00]
+ rx_buffer = spi.xfer2(spi_buffer)
+ print(f"Spi readback register 0x03: 0x{rx_buffer[1]:02x}")
+ if rx_buffer[1] != high_word:
+ print("Different value read than sent in reg 0x03")
+
+ # REGISTER A4
+ # test pattern low word
+ spi_buffer = [0x04, low_word]
+ spi.xfer2(spi_buffer)
+
+ # read balues back
+ spi_buffer = [0x84, 0x00]
+ rx_buffer = spi.xfer2(spi_buffer)
+ print(f"Spi readback register 0x04: 0x{rx_buffer[1]:02x}")
+ if rx_buffer[1] != low_word:
+ print("Different value read than sent in reg 0x04")
+ finally:
+ spi.close()
+
+
+def main_adc_test_mode(enable):
+ spi = spidev.SpiDev()
+
+ try:
+ spi.open(MAIN_ADC_BUS, MAIN_ADC_DEVICE)
+ spi.max_speed_hz = 50000
+ spi.mode = 0b00 # CPOL = 0 CPHA = 0
+ spi.cshigh = False
+ # spi.read0 = True
+
+ reg_contents = (
+ 0x15 if enable else 0x11
+ ) # set to LVDS output, set 4 data lanes and turn on or off test mode
+ spi_buffer = [0x02, reg_contents]
+ spi.xfer2(spi_buffer)
+
+ # read values back
+ spi_buffer = [0x82, 0x00]
+ rx_buffer = spi.xfer2(spi_buffer)
+ print(f"Spi readback register 0x02: 0x{rx_buffer[1]:02x}")
+ if rx_buffer[1] != reg_contents:
+ print("Different value read than sent in reg 0x02")
+ finally:
+ spi.close()
+
+
+def read_from_memory(address, n_bytes):
+ assert n_bytes <= 4
+ addr = address
+
+ try:
+ f = os.open("/dev/mem", os.O_SYNC | os.O_RDWR)
+ with mmap.mmap(
+ f,
+ PAGESIZE,
+ mmap.MAP_SHARED,
+ mmap.PROT_READ | mmap.PROT_WRITE,
+ offset=addr & ~MAP_MASK,
+ ) as mem:
+ start_addr = addr & MAP_MASK
+ stop_addr = start_addr + 4
+ # print(f"addr: 0x{addr:x}\tstart_addr: 0x{start_addr}\tstop_addr: 0x{stop_addr}")
+ contents = mem[start_addr:stop_addr]
+ read_value = list(contents)[:n_bytes]
+ # print("Read value: ", read_value)
+ finally:
+ os.close(f)
+
+ return read_value
+
+
+def write_to_memory(address, value):
+ value_bytes = value.to_bytes(4, "little")
+ addr = address
+
+ try:
+ f = os.open("/dev/mem", os.O_SYNC | os.O_RDWR)
+ with mmap.mmap(
+ f,
+ PAGESIZE,
+ mmap.MAP_SHARED,
+ mmap.PROT_READ | mmap.PROT_WRITE,
+ offset=addr & ~MAP_MASK,
+ ) as mem:
+ start_addr = addr & MAP_MASK
+ stop_addr = start_addr + 4
+ # print(f"addr: 0x{addr:x}\tstart_addr: 0x{start_addr}\tstop_addr: 0x{stop_addr}")
+ mem[start_addr:stop_addr] = value_bytes
+ contents = mem[start_addr:stop_addr]
+ # print("Read value: ", list(contents), " written value: ", list(value_bytes))
+ finally:
+ os.close(f)
+
+
+def word_align():
+
+ value = 0
+ edge_detected = False
+ transition = False
+ tap_delay = 0
+
+ for i in range(4):
+ current_frame = read_from_memory(ADC_FRAME_ADDR, 1)[0]
+ if current_frame != 0x0C:
+ print(
+ f"Performing bitslip (bitslip iteration: {i}). Reason: current_frame is 0x{current_frame:02x} instead of 0x0C"
+ )
+ write_to_memory(ADC_BITSLIP_ADDR, 1)
+ else:
+ print(f"No bitslip required; Currernt frame = 0x{current_frame:02x}")
+ break
+
+ current_frame = read_from_memory(ADC_FRAME_ADDR, 1)[0]
+ prev_frame = current_frame
+
+ for i in range(32):
+ write_to_memory(ADC_DELAY_ADDR, tap_delay)
+ if edge_detected == 1:
+ break
+ current_frame = read_from_memory(ADC_FRAME_ADDR, 1)[0]
+
+ print(f"Tap delay: {tap_delay}")
+ print(f"Current frame: 0x{current_frame:02x}")
+
+ if current_frame == prev_frame:
+ tap_delay += 1
+ elif not transition:
+ tap_delay += 1
+ transition = True
+ elif transition:
+ tap_delay = i // 2
+ edge_detected = True
+
+ prev_frame = current_frame
+
+ if not edge_detected:
+ tap_delay = 11 # empirically tested to work best
+ write_to_memory(ADC_DELAY_ADDR, tap_delay)
+ print(f"No edge detected; setting iDelay to: {tap_delay}")
+ if edge_detected:
+ write_to_memory(ADC_DELAY_ADDR, tap_delay + 2)
+ print(f"Edge detected; setting iDelay to (tap_delay + 2): {tap_delay} + 2")
+
+ adc_ch0 = read_from_memory(ADC_CH0_HIGH_ADDR, 4)
+ print(f"ADC_CH0: 0x{adc_ch0}")
+
+ adc_ch0 = (read_from_memory(ADC_CH0_HIGH_ADDR, 1)[0] << 8) | read_from_memory(
+ ADC_CH0_LOW_ADDR, 1
+ )[0]
+ adc_ch1 = (read_from_memory(ADC_CH1_HIGH_ADDR, 1)[0] << 8) | read_from_memory(
+ ADC_CH1_LOW_ADDR, 1
+ )[0]
+ print(f"Final ADC_CH0: 0x{adc_ch0:04x}")
+ print(f"Final ADC_CH1: 0x{adc_ch1:04x}")
+
+
+def modify_bit(original_value, position, bit_value):
+ mask = 1 << position
+ return (original_value & ~mask) | (bit_value << position)
+
+
+def adc_aux_config():
+ # MSB to LSB
+ # | RANGE | ADDR [2:0] | DIFF |
+ # DIFF = 0 => configure as single ended (it is negated in gateware)
+ # RANGE = 0 => configure as 0-2.5 Vref
+ to_write = 0b00000
+ write_to_memory(AUX_ADC_ADDR, to_write)
+
+
+def adc_aux_read(port, type, pin):
+ # port:
+ # 1 - port A
+ # 2 - port B
+ # type:
+ # 0 - single-ended
+ # 1 - differential
+ # pin:
+ # 0b000 - VA1/VB1
+ # 0b001 - VA2/VB2
+ # 0b010 - VA3/VB3
+ # 0b011 - VA4/VB4
+
+ assert type in (0, 1)
+ assert port in (1, 2)
+
+ write_buffer = [0, 0]
+ read_buffer = [0, 0]
+
+ aux_config_reg = read_from_memory(AUX_ADC_ADDR, 1)[0]
+ aux_config = (aux_config_reg & 0b10001) | pin << 1
+ write_to_memory(AUX_ADC_ADDR, aux_config)
+
+ spi = spidev.SpiDev()
+ try:
+ spi.open(1, 3) # AUX ADC 1?
+ spi.max_speed_hz = 5000
+ spi.mode = 0b00
+ spi.cshigh = False
+
+ read_buffer = spi.xfer2(write_buffer)
+ mu_voltage = read_buffer[0] << 8 | read_buffer[1] >> 2
+ print(f"MU_voltage: 0x{mu_voltage:04X}")
+ print(f"Read_buffer[0]: 0x{read_buffer[0]:02X}")
+ print(f"Read_buffer[1]: 0x{read_buffer[1]:02X}")
+ return mu_voltage * 2.5 / 4096
finally:
spi.close()
+
+def main():
+ main_adc_config(0x811F)
+ word_align()
+
+ main_adc_test_mode(False)
+
+ write_to_memory(ADC_AFE_CTRL_ADDR, 0b1100) # {-, -, ch2_X10, ch1_X10}
+ print(read_from_memory(ADC_AFE_CTRL_ADDR, 1)[0])
+
+
if __name__ == "__main__":
- configure_ltc2195()
\ No newline at end of file
+ main()
\ No newline at end of file
diff --git a/fast-servo/pyfastservo/common.py b/fast-servo/pyfastservo/common.py
index 40a5121..dbf60ab 100644
--- a/fast-servo/pyfastservo/common.py
+++ b/fast-servo/pyfastservo/common.py
@@ -17,9 +17,6 @@
# You should have received a copy of the GNU General Public License
# along with this program. If not, see .
-import os
-import mmap
-
CSR_SIZE = 0x800
MAP_SIZE = 0x1000
MAP_MASK = 0xFFF
@@ -74,47 +71,4 @@ CTRL_ADDR = DAC_BASE_ADDR + CTRL_OFFSET
CH0_HIGH_WORD_ADDR = DAC_BASE_ADDR + CH0_HIGH_WORD_OFFSET
CH0_LOW_WORD_ADDR = DAC_BASE_ADDR + CH0_LOW_WORD_OFFSET
CH1_HIGH_WORD_ADDR = DAC_BASE_ADDR + CH1_HIGH_WORD_OFFSET
-CH1_LOW_WORD_ADDR = DAC_BASE_ADDR + CH1_LOW_WORD_OFFSET
-
-
-def read_from_memory(address, n_bytes):
- assert n_bytes <= 4
- addr = address
-
- try:
- f = os.open("/dev/mem", os.O_SYNC | os.O_RDWR)
- with mmap.mmap(
- f,
- PAGESIZE,
- mmap.MAP_SHARED,
- mmap.PROT_READ | mmap.PROT_WRITE,
- offset=addr & ~MAP_MASK,
- ) as mem:
- start_addr = addr & MAP_MASK
- stop_addr = start_addr + 4
- contents = mem[start_addr:stop_addr]
- read_value = list(contents)[:n_bytes]
- finally:
- os.close(f)
-
- return read_value
-
-def write_to_memory(address, value):
- value_bytes = value.to_bytes(4, "little")
- addr = address
-
- try:
- f = os.open("/dev/mem", os.O_SYNC | os.O_RDWR)
- with mmap.mmap(
- f,
- PAGESIZE,
- mmap.MAP_SHARED,
- mmap.PROT_READ | mmap.PROT_WRITE,
- offset=addr & ~MAP_MASK,
- ) as mem:
- start_addr = addr & MAP_MASK
- stop_addr = start_addr + 4
- mem[start_addr:stop_addr] = value_bytes
- contents = mem[start_addr:stop_addr]
- finally:
- os.close(f)
\ No newline at end of file
+CH1_LOW_WORD_ADDR = DAC_BASE_ADDR + CH1_LOW_WORD_OFFSET
\ No newline at end of file
diff --git a/fast-servo/pyfastservo/dac.py b/fast-servo/pyfastservo/dac.py
index cb9d5a7..a523ffc 100644
--- a/fast-servo/pyfastservo/dac.py
+++ b/fast-servo/pyfastservo/dac.py
@@ -17,7 +17,8 @@
# You should have received a copy of the GNU General Public License
# along with this program. If not, see .
-import time
+import mmap
+import os
import spidev
from pyfastservo.common import (
@@ -28,58 +29,108 @@ from pyfastservo.common import (
CTRL_ADDR,
MAP_MASK,
PAGESIZE,
- write_to_memory,
- read_from_memory
)
# /dev/spidev2.0 <=> spidev.
MAIN_DAC_BUS = 2
MAIN_DAC_DEVICE = 0
+
DAC_VERSION = 0x0A
-def spi_write(spi, address, value):
- spi.xfer2([address, value])
+def main_dac_init():
+ spi = spidev.SpiDev()
-def spi_read(spi, address):
- rx_buffer = spi.xfer2([0x80 | address, 0x00])
- return rx_buffer[1]
+ try:
+ spi.open(MAIN_DAC_BUS, MAIN_DAC_DEVICE)
+ spi.max_speed_hz = 5000
+ spi.mode = 0b00 # CPOL = 0 CPHA = 0
+ spi.cshigh = False
-def hard_reset(spi):
- spi_write(spi, 0x00, 0x20) # Software reset
- spi_write(spi, 0x00, 0x00) # Release software reset
- spi_read(spi, 0x00) # Read reset address (necessary for reset to take effect)
+ spi_buffer = [0x00, 0x10] # software reset
+ spi.xfer2(spi_buffer)
-def check_version(spi):
- version = spi_read(spi, 0x1F)
- print(f"DAC version: 0x{version:02X}")
- return version == DAC_VERSION
+ spi_buffer = [0x00, 0x00] # release software reset
+ spi.xfer2(spi_buffer)
-def configure_dac(spi):
- power_down_reg = spi_read(spi, 0x01)
- spi_write(spi, 0x01, power_down_reg & ~(1 << 0)) # Clear EXTREF bit for internal reference
- spi_write(spi, 0x0D, 0x00) # Set RREF to 10 kΩ for 1.0V reference
- spi_write(spi, 0x04, 0xA0) # Enable on-chip IRSET (1.6 kΩ for 20mA output)
- spi_write(spi, 0x07, 0xA0) # Enable on-chip QRSET (1.6 kΩ for 20mA output)
- spi_write(spi, 0x05, 0x00) # Disable internal IRCML
- spi_write(spi, 0x08, 0x00) # Disable internal QRCML
- spi_write(spi, 0x02, 0xB4) # Enable 2's complement, LVDS interface, 4 LVDS lanes
+ spi_buffer = [
+ 0x80,
+ 0x00,
+ ] # for some reason it is needed to read the reset address for reset to actually reset
+ rx_buffer = spi.xfer2(spi_buffer)
-def dac_self_calibration(spi):
- spi_write(spi, 0x12, 0x00) # Reset calibration status
- spi_write(spi, 0x0E, 0x08) # Enable calibration clock, default divide ratio
- spi_write(spi, 0x0E, 0x38) # CALSELI = 1, CALSELQ = 1, CALCLK = 1
- spi_write(spi, 0x12, 0x10) # Set CALEN bit
+ spi_buffer = [0x9F, 0x00] # hardware version
+ rx_buffer = spi.xfer2(spi_buffer)
+ if rx_buffer[1] != DAC_VERSION:
+ print(f"Unrecognized device: 0x{rx_buffer[1]:02X}")
- while True:
- status = spi_read(spi, 0x0F)
- if status & 0xC0 == 0xC0: # Both CALSTATI and CALSTATQ are 1
- break
- time.sleep(0.01)
+ print("=== Contents of spi buffer after DAC VERSION read back: ===")
+ print(f"0x{rx_buffer[0]:02X}{rx_buffer[1]:02X}")
+
+ spi_buffer = [0x82, 00]
+ rx_buffer = spi.xfer2(spi_buffer)
+ print(f"0x{rx_buffer[0]:02X}{rx_buffer[1]:02X}")
+
+ # set to 2's complement and I to be first of pair on data input pads
+ spi_buffer = [0x02, 0xB4]
+ rx_buffer = spi.xfer2(spi_buffer)
+ spi_buffer = [0x82, 00]
+ rx_buffer = spi.xfer2(spi_buffer)
+ print(f"0x{rx_buffer[0]:02X}{rx_buffer[1]:02X}")
+
+ for i in range(10):
+ spi_buffer = [0x94, 0x00]
+ rx_buffer = spi.xfer2(spi_buffer)
+ print(f"0x{rx_buffer[0]:02X}{rx_buffer[1]:02X}")
+
+ finally:
+ spi.close()
+
+
+def read_from_memory(address, n_bytes):
+ assert n_bytes <= 4
+ addr = address
+
+ try:
+ f = os.open("/dev/mem", os.O_SYNC | os.O_RDWR)
+ with mmap.mmap(
+ f,
+ PAGESIZE,
+ mmap.MAP_SHARED,
+ mmap.PROT_READ | mmap.PROT_WRITE,
+ offset=addr & ~MAP_MASK,
+ ) as mem:
+ start_addr = addr & MAP_MASK
+ stop_addr = start_addr + 4
+ # print(f"addr: 0x{addr:x}\tstart_addr: 0x{start_addr}\tstop_addr: 0x{stop_addr}")
+ contents = mem[start_addr:stop_addr]
+ read_value = list(contents)[:n_bytes]
+ finally:
+ os.close(f)
+
+ return read_value
+
+
+def write_to_memory(address, value):
+ value_bytes = value.to_bytes(4, "little")
+ addr = address
+
+ try:
+ f = os.open("/dev/mem", os.O_SYNC | os.O_RDWR)
+ with mmap.mmap(
+ f,
+ PAGESIZE,
+ mmap.MAP_SHARED,
+ mmap.PROT_READ | mmap.PROT_WRITE,
+ offset=addr & ~MAP_MASK,
+ ) as mem:
+ start_addr = addr & MAP_MASK
+ stop_addr = start_addr + 4
+ mem[start_addr:stop_addr] = value_bytes
+ contents = mem[start_addr:stop_addr]
+ finally:
+ os.close(f)
- spi_write(spi, 0x12, 0x00) # Clear calibration bits
- spi_write(spi, 0x0E, 0x30) # Keep CALSELI and CALSELQ set, clear CALCLK
- print("DAC self-calibration completed")
def manual_override(enable=True):
reg_contents = read_from_memory(CTRL_ADDR, 1)[0]
@@ -87,6 +138,7 @@ def manual_override(enable=True):
to_write = reg_contents | 0b1 if enable else reg_contents & 0b110
write_to_memory(CTRL_ADDR, to_write)
+
def power_down(channel, power_down=True):
assert channel in (0, 1)
@@ -100,49 +152,31 @@ def power_down(channel, power_down=True):
reg_contents = read_from_memory(CTRL_ADDR, 1)[0]
print(f"REG contents: 0b{reg_contents:03b}")
-def set_dac_output(value):
- value = min(value, 0x3FFF)
- low_word = value & 0xFF
- high_word = (value >> 8) & 0x3F
- write_to_memory(CH0_HIGH_WORD_ADDR, high_word)
- write_to_memory(CH0_LOW_WORD_ADDR, low_word)
- write_to_memory(CH1_HIGH_WORD_ADDR, high_word)
- write_to_memory(CH1_LOW_WORD_ADDR, low_word)
- print(f"DAC output set to: 0x{value:04X}")
+def write_sample(channel, sample):
+ assert channel in (0, 1)
+ if channel == 0:
+ addresses = [CH0_HIGH_WORD_ADDR, CH0_LOW_WORD_ADDR]
+ else:
+ addresses = [CH1_HIGH_WORD_ADDR, CH1_LOW_WORD_ADDR]
-def configure_ad9117():
- spi = spidev.SpiDev()
- spi.open(MAIN_DAC_BUS, MAIN_DAC_DEVICE)
- spi.max_speed_hz = 5000
- spi.mode = 0b00 # CPOL = 0 CPHA = 0
- spi.cshigh = False
+ low_word_value = sample & 0xFF
+ high_word_value = (sample >> 8) & 0x3F
+ values = [high_word_value, low_word_value]
+ for addr, value in zip(addresses, values):
+ write_to_memory(addr, value)
- try:
- hard_reset(spi)
- if not check_version(spi):
- print("Unrecognized DAC version")
- return False
- configure_dac(spi)
- # dac_self_calibration(spi)
+def write_ramp():
+ signal = [i for i in range(16384)]
- # Enable DAC outputs
- spi_write(spi, 0x01, spi_read(spi, 0x01) & ~((1 << 4) | (1 << 3)))
-
- power_down(0, False)
- power_down(1, False)
- manual_override(True)
-
- print("AD9117 configuration completed successfully")
- return True
-
- except Exception as e:
- print(f"Error configuring AD9117: {e}")
- return False
-
- finally:
- spi.close()
+ for value in signal:
+ write_sample(0, value)
+def main():
+ main_dac_init()
+ power_down(0, False)
+ power_down(1, False)
+
if __name__ == "__main__":
- configure_ad9117()
\ No newline at end of file
+ main()
\ No newline at end of file
diff --git a/fast-servo/pyfastservo/initialize.py b/fast-servo/pyfastservo/initialize.py
index 19529a6..9adeb2b 100644
--- a/fast-servo/pyfastservo/initialize.py
+++ b/fast-servo/pyfastservo/initialize.py
@@ -21,8 +21,8 @@ from pyfastservo import adc, si5340, dac
def main():
si5340.configure_si5340()
- adc.configure_ltc2195()
- dac.configure_ad9117()
+ adc.main()
+ dac.main()
if __name__ == "__main__":
main()
\ No newline at end of file
diff --git a/fast-servo/pyfastservo/loopback.py b/fast-servo/pyfastservo/loopback.py
index 6edfb1d..dcf2c16 100644
--- a/fast-servo/pyfastservo/loopback.py
+++ b/fast-servo/pyfastservo/loopback.py
@@ -1,60 +1,48 @@
-import time
-from pyfastservo import adc, dac
-from pyfastservo.common import (
- ADC_CH0_HIGH_ADDR, ADC_CH0_LOW_ADDR,
- ADC_CH1_HIGH_ADDR, ADC_CH1_LOW_ADDR,
- CH0_HIGH_WORD_ADDR, CH0_LOW_WORD_ADDR,
- CH1_HIGH_WORD_ADDR, CH1_LOW_WORD_ADDR,
- read_from_memory, write_to_memory
+# This file is part of Fast Servo Software Package.
+#
+# Copyright (C) 2023 Jakub Matyas
+# Warsaw University of Technology
+# SPDX-License-Identifier: GPL-3.0-or-later
+
+from pyfastservo.dac import (
+ CH0_HIGH_WORD_ADDR,
+ CH0_LOW_WORD_ADDR,
+ CH1_HIGH_WORD_ADDR,
+ CH1_LOW_WORD_ADDR,
+ write_sample,
+ manual_override,
+ read_from_memory as dac_read_from_memory
+)
+from pyfastservo.adc import (
+ ADC_CH0_HIGH_ADDR,
+ ADC_CH0_LOW_ADDR,
+ ADC_CH1_HIGH_ADDR,
+ ADC_CH1_LOW_ADDR,
+ read_from_memory as adc_read_from_memory
)
-def read_adc(channel):
- if channel == 0:
- return adc.read_adc_channel(ADC_CH0_HIGH_ADDR, ADC_CH0_LOW_ADDR)
- elif channel == 1:
- return adc.read_adc_channel(ADC_CH1_HIGH_ADDR, ADC_CH1_LOW_ADDR)
- else:
- raise ValueError("Invalid ADC channel")
-
-def write_dac(value):
- dac.set_dac_output(value)
-
-def read_dac(channel):
- if channel == 0:
- high_word = read_from_memory(CH0_HIGH_WORD_ADDR, 1)[0]
- low_word = read_from_memory(CH0_LOW_WORD_ADDR, 1)[0]
- elif channel == 1:
- high_word = read_from_memory(CH1_HIGH_WORD_ADDR, 1)[0]
- low_word = read_from_memory(CH1_LOW_WORD_ADDR, 1)[0]
- else:
- raise ValueError("Invalid DAC channel")
- return (high_word << 8) | low_word
-
-def perform_loopback_test(test_value):
- print(f"\nSetting DAC output to {test_value}...")
- write_dac(test_value)
- time.sleep(0.1) # Allow time for the signal to stabilize
-
- for channel in [0, 1]:
- print(f"\nTesting Channel {channel}")
-
- print(f"Reading ADC CH{channel} value...")
- adc_value = read_adc(channel)
- print(f"ADC CH{channel} readback: {adc_value}")
-
- print(f"Reading DAC CH{channel} value...")
- dac_value = read_dac(channel)
- print(f"DAC CH{channel} readback: {dac_value}")
-
- if abs(test_value - adc_value) <= 2 and abs(test_value - dac_value) <= 2:
- print(f"Loopback test for Channel {channel} PASSED!")
- else:
- print(f"Loopback test for Channel {channel} FAILED!")
- print(f"Expected: {test_value}, ADC: {adc_value}, DAC: {dac_value}")
-#
def main():
- test_value = 0x0FFF # Mid-range value (4095 in decimal)
- perform_loopback_test(test_value)
+ # Apply manual override for DAC
+ manual_override(True)
+
+ # Write constant value to DAC channels
+ constant_value = 0x1FFF
+ write_sample(0, constant_value)
+ write_sample(1, constant_value)
+
+ # Verify DAC register values
+ dac_ch0 = (dac_read_from_memory(CH0_HIGH_WORD_ADDR, 1)[0] << 8) | dac_read_from_memory(CH0_LOW_WORD_ADDR, 1)[0]
+ dac_ch1 = (dac_read_from_memory(CH1_HIGH_WORD_ADDR, 1)[0] << 8) | dac_read_from_memory(CH1_LOW_WORD_ADDR, 1)[0]
+
+ print(f"DAC CH0: 0x{dac_ch0:04X}")
+ print(f"DAC CH1: 0x{dac_ch1:04X}")
+
+ # Read ADC values
+ adc_ch0 = (adc_read_from_memory(ADC_CH0_HIGH_ADDR, 1)[0] << 8) | adc_read_from_memory(ADC_CH0_LOW_ADDR, 1)[0]
+ adc_ch1 = (adc_read_from_memory(ADC_CH1_HIGH_ADDR, 1)[0] << 8) | adc_read_from_memory(ADC_CH1_LOW_ADDR, 1)[0]
+
+ print(f"ADC CH0: 0x{adc_ch0:04X}")
+ print(f"ADC CH1: 0x{adc_ch1:04X}")
if __name__ == "__main__":
main()
\ No newline at end of file