gateware: Add cdc fifo for adc and dac

- dco2d and sys clk use two different clock sources

fast-servo/linien-gateware/cores/adc.py

@@ -20,6 +20,7 @@
 from migen import *
 from migen.genlib.cdc import MultiReg
 from misoc.interconnect.csr import AutoCSR, CSRStatus, CSRStorage
+from misoc.interconnect.stream import AsyncFIFO
 
 
 class CRG(Module):
@@ -130,7 +131,17 @@ class ADC(Module, AutoCSR):
         ch2_shdn = Signal()
 
         self.data_out = [Signal(16, reset_less=True), Signal(16, reset_less=True)]
+        self.data_out_cdc = [Signal(16, reset_less=True), Signal(16, reset_less=True)]
         self.s_frame = Signal(4)
+        self.s_frame_cdc = Signal(4)
+
+        self.submodules.cdc_fifo = ClockDomainsRenamer({"write": "dco2d", "read": "sys"})(AsyncFIFO([("data", 36)], 2))
+        self.comb += [
+            self.cdc_fifo.sink.data.eq(Cat(self.data_out_cdc[0], self.data_out_cdc[1], self.s_frame_cdc)),
+            self.cdc_fifo.sink.stb.eq(~ResetSignal("dco2d")),
+            Cat(self.data_out[0], self.data_out[1], self.s_frame).eq(self.cdc_fifo.source.data),
+            self.cdc_fifo.source.ack.eq(~ResetSignal("sys")),
+        ]
 
         ###
 
@@ -187,9 +198,9 @@ class ADC(Module, AutoCSR):
             i_D1_in_n=adc_pads.data1_n,
             i_bitslip=bitslip,
             i_delay_val=tap_delay_val,
-            o_ADC0_out=self.data_out[1],        # LANES swapped on hardware
+            o_ADC0_out=self.data_out_cdc[1],        # LANES swapped on hardware
-            o_ADC1_out=self.data_out[0],
+            o_ADC1_out=self.data_out_cdc[0],
-            o_FR_out=self.s_frame,
+            o_FR_out=self.s_frame_cdc,
             o_o_data_from_pins=dummy,
             o_idelay_rdy=dummy_idelay_rdy,
         )

fast-servo/linien-gateware/cores/dac.py

@@ -20,6 +20,7 @@
 from migen import *
 from misoc.interconnect.csr import AutoCSR, CSRStorage
 from migen.genlib.io import DDROutput
+from misoc.interconnect.stream import AsyncFIFO
 
 
 class DAC(Module, AutoCSR):
@@ -38,18 +39,27 @@ class DAC(Module, AutoCSR):
         output_data_ch1 = Signal(14)
 
         self.data_in = [Signal(14, reset_less=True), Signal(14, reset_less=True)]
+        self.data_in_cdc = [Signal(14, reset_less=True), Signal(14, reset_less=True)]
         platform.add_period_constraint(dac_pads.dclkio, 10.0)
 
+        self.submodules.cdc_fifo = ClockDomainsRenamer({"write": "sys", "read": "dco2d"})(AsyncFIFO([("data", 28)], 2))
+        self.comb += [
+            self.cdc_fifo.sink.data.eq(Cat(self.data_in[0], self.data_in[1])),
+            self.cdc_fifo.sink.stb.eq(~ResetSignal("sys")),
+            Cat(self.data_in_cdc[0], self.data_in_cdc[1]).eq(self.cdc_fifo.source.data),
+            self.cdc_fifo.source.ack.eq(~ResetSignal("dco2d")),
+        ]
+
         self.comb += [
             Cat(manual_override, ch0_pd, ch1_pd).eq(self.dac_ctrl.storage),
             dac_pads.rst.eq(ResetSignal("dco2d")),
             dac_afe_pads.ch1_pd_n.eq(~ch0_pd),
             dac_afe_pads.ch2_pd_n.eq(~ch1_pd),
             output_data_ch0.eq(
-                Mux(manual_override, self.output_value_ch0.storage, self.data_in[0])
+                Mux(manual_override, self.output_value_ch0.storage, self.data_in_cdc[0])
             ),
             output_data_ch1.eq(
-                Mux(manual_override, self.output_value_ch1.storage, self.data_in[1])
+                Mux(manual_override, self.output_value_ch1.storage, self.data_in_cdc[1])
             ),
         ]
 

fast-servo/linien-gateware/fast_servo_soc.py

@@ -147,6 +147,7 @@ class BaseSoC(PS7, AutoCSR):
         # self.add_main_adc(platform)
         self.submodules.adc = ADC(platform)
         self.csr_devices.append("adc")
+        platform.add_false_path_constraints(self.crg.cd_sys.clk, self.adc.crg.cd_dco2d.clk)
 
         # self.add_main_dac(platform)
         self.submodules.dac = DAC(platform)