forked from M-Labs/nix-servo
Update PL init scripts
- Cleanup - Better debugging message - Adjust Dac Init sequence so that it always outputs 0V during init
This commit is contained in:
parent
4a3fe50427
commit
04c8e7b58e
@ -54,28 +54,42 @@ def spi_read(spi, address):
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def main_adc_config(spi, test_pattern):
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high_word = (test_pattern & 0xFF00) >> 8
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low_word = test_pattern & 0xFF
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register_settings = {
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0x01: 0x20, # REGISTER A1: set to Two's complement Data Format
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0x02: 0x11, # REGISTER A2: set to LVDS output, set 4 data lanes
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0x03: high_word, # REGISTER A3: test pattern high word
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0x04: low_word, # REGISTER A4: test pattern low word
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}
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spi_write(spi, 0x00, 0x80) # reset
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spi_write(spi, 0x01, 0x20) # REGISTER A1: set to Two's complement Data Format
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spi_write(spi, 0x02, 0x15) # REGISTER A2: set to LVDS output, set 4 data lanes and turn on test mode
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spi_write(spi, 0x03, high_word) # REGISTER A3: test pattern high word
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spi_write(spi, 0x04, low_word) # REGISTER A4: test pattern low word
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spi_write(spi, 0x00, 0x80) # Soft Reset
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for addr, val in register_settings.items():
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spi_write(spi, addr, val)
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return verify_registers_vals(spi, register_settings)
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def main_adc_test_mode(spi, enable):
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reg_contents = 0x15 if enable else 0x11 # set to LVDS output, set 4 data lanes and turn on or off test mode
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spi_write(spi, 0x02, reg_contents)
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value = spi_read(spi, 0x02)
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# set to LVDS output, set 4 data lanes and turn on or off test mode
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if enable:
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value |= 1 << 2
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else:
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value &= 0xfb
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def verify_adc_registers(spi, reg_to_check):
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spi_write(spi, 0x02, value)
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return verify_registers_vals(spi, {0x02: value})
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def verify_registers_vals(spi, reg_to_check):
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for register, expected_value in reg_to_check.items():
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value = spi_read(spi, register)
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print(f"Spi readback register 0x{register:02x}: 0x{value:02x}")
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if value != expected_value:
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print(f"Different value read than sent in reg 0x{register:02x}")
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print(f"Different value read than sent in reg 0x{register:02x}. Expected: 0x{expected_value:02x} Got: 0x{value:02x}")
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return False
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return True
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def read_frame():
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return read_from_memory(ADC_FRAME_ADDR, 1)[0]
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def perform_bitslip():
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def perform_word_alignment():
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for i in range(4):
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current_frame = read_frame()
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if current_frame & 0x0F != 0x0C:
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@ -83,9 +97,8 @@ def perform_bitslip():
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write_to_memory(ADC_BITSLIP_ADDR, 1)
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else:
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print(f"No bitslip required; Current frame: 0x{current_frame:02x}")
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return
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break
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def find_edge():
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prev_frame = read_frame()
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for tap_delay in range(32):
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write_to_memory(ADC_DELAY_ADDR, tap_delay)
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@ -98,40 +111,32 @@ def find_edge():
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final_delay = ((tap_delay+1) // 2) + 2
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print(f"Edge detected; setting iDelay to: {final_delay}")
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write_to_memory(ADC_DELAY_ADDR, final_delay)
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return
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return True
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prev_frame = current_frame
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# If no edge detected
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final_delay = 11
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print(f"No edge detected; setting iDelay to: {final_delay}")
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write_to_memory(ADC_DELAY_ADDR, final_delay)
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return False
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def read_adc_channel(high_addr, low_addr):
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return (read_from_memory(high_addr, 1)[0] << 8) | read_from_memory(low_addr, 1)[0]
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def print_adc_channels():
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adc_ch0 = read_adc_channel(ADC_CH0_HIGH_ADDR, ADC_CH0_LOW_ADDR)
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adc_ch1 = read_adc_channel(ADC_CH1_HIGH_ADDR, ADC_CH1_LOW_ADDR)
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print(f"Final ADC_CH0: 0x{adc_ch0:04x}")
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print(f"Final ADC_CH1: 0x{adc_ch1:04x}")
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def is_clk_aligned(spi, test_pattern):
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aligned = True
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main_adc_test_mode(spi, True)
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for i in range(100):
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adc_ch0 = read_adc_channel(ADC_CH0_HIGH_ADDR, ADC_CH0_LOW_ADDR)
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adc_ch1 = read_adc_channel(ADC_CH1_HIGH_ADDR, ADC_CH1_LOW_ADDR)
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if adc_ch0 != test_pattern or adc_ch1 != test_pattern:
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aligned = False
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break
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main_adc_test_mode(spi, False)
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return aligned
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def enable_adc_afe(ch1_x10=False, ch2_x10=False):
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ctrl_value = (ch2_x10 << 1) | ch1_x10
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write_to_memory(ADC_AFE_CTRL_ADDR, ctrl_value)
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afe_ctrl = read_from_memory(ADC_AFE_CTRL_ADDR, 1)[0]
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print(f"ADC_AFE_CTRL: 0x{afe_ctrl:02X}")
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print(f"Configure ADC AFE Gain: ch1_10x: {"10x" if ch1_x10 else "1x"} | ch2_x10: {"10x" if ch2_x10 else "1x"}")
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return afe_ctrl
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def search_edge():
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for tap_delay in range(32):
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print(f"iDelay to: {tap_delay}")
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write_to_memory(ADC_DELAY_ADDR, tap_delay)
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time.sleep(1)
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current_frame = read_frame()
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print(f"Tap delay: {tap_delay}, Current frame: 0x{current_frame:02x}")
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print_adc_channels()
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def print_adc_channel(ch):
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if ch == 0:
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adc_ch0 = read_adc_channel(ADC_CH0_HIGH_ADDR, ADC_CH0_LOW_ADDR)
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@ -140,62 +145,37 @@ def print_adc_channel(ch):
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adc_ch1 = read_adc_channel(ADC_CH1_HIGH_ADDR, ADC_CH1_LOW_ADDR)
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print(f"Final ADC_CH1: 0x{adc_ch1:04x}")
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def find_min_max_ch(ch):
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test = []
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for i in range(100):
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if ch == 0:
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test.append(read_adc_channel(ADC_CH0_HIGH_ADDR, ADC_CH0_LOW_ADDR))
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else:
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test.append(read_adc_channel(ADC_CH1_HIGH_ADDR, ADC_CH1_LOW_ADDR))
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print("ch", ch, hex(test[-1]))
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print("Min:", hex(min(test)))
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print("Max:", hex(max(test)))
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print("Diff:", hex(max(test)-min(test)))
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def configure_ltc2195():
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print()
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print("### Initializing LTC2195 Adc")
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spi = spidev.SpiDev()
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spi.open(MAIN_ADC_BUS, MAIN_ADC_DEVICE)
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spi.max_speed_hz = 50000
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spi.mode = 0b00 # CPOL = 0 CPHA = 0
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spi.cshigh = False
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success = True
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try:
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spi.open(MAIN_ADC_BUS, MAIN_ADC_DEVICE)
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spi.max_speed_hz = 50000
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spi.mode = 0b00 # CPOL = 0 CPHA = 0
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spi.cshigh = False
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test_pattern = 0x811F
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main_adc_config(spi, test_pattern)
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verify_adc_registers(spi, {
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0x01: 0x20,
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0x02: 0x15,
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0x03: (test_pattern & 0xFF00) >> 8,
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0x04: test_pattern & 0xFF
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})
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success &= main_adc_config(spi, test_pattern)
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# Performing Word Align
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perform_bitslip()
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find_edge()
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# Printing it once is not enough to check whether the alignment is correct.
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for i in range(100):
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print_adc_channels()
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main_adc_test_mode(spi, False)
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verify_adc_registers(spi, {0x02: 0x11}) # Verify test mode is off
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# FIXME: AFE Gain 1x is not functional on that batch of fast servo under development
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enable_adc_afe(ch1_x10=1, ch2_x10=1)
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#find_min_max_ch(0)
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#find_min_max_ch(1)
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#for i in range(10):
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# print_adc_channel(0)
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#for i in range(10):
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# print_adc_channel(1)
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success &= perform_word_alignment()
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if is_clk_aligned(spi, test_pattern):
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print("PL Data and Clock Alignment is verified")
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else:
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success &= False
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print("Error: Clocks are not aligned")
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enable_adc_afe(ch1_x10=0, ch2_x10=0)
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except Exception as e:
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print(f"Error configuring LTC2195: {e}")
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success = False
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finally:
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spi.close()
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if success:
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print("LTC2195 Adc init completed")
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else:
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print("LTC2195 Adc init failed")
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return success
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if __name__ == "__main__":
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configure_ltc2195()
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@ -56,6 +56,14 @@ def spi_read(spi, address):
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rx_buffer = spi.xfer2([0x80 | address, 0x00])
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return rx_buffer[1]
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def verify_registers_vals(spi, reg_to_check):
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for register, expected_value in reg_to_check.items():
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value = spi_read(spi, register)
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if value != expected_value:
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print(f"Different value read than sent in reg 0x{register:02x}. Expected: 0x{expected_value:02x} Got: 0x{value:02x}")
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return False
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return True
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def soft_reset(spi):
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spi_write(spi, 0x00, 0x10) # Software reset
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spi_write(spi, 0x00, 0x00) # Release software reset
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@ -67,17 +75,22 @@ def check_version(spi):
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return version == DAC_VERSION
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def configure_dac(spi):
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power_down_reg = spi_read(spi, 0x01)
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spi_write(spi, 0x01, power_down_reg & ~(1 << 0)) # Clear EXTREF bit for internal reference
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spi_write(spi, 0x0D, 0x00) # Set RREF to 10 kΩ for 1.0V reference
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spi_write(spi, 0x04, 0xA0) # Enable on-chip IRSET (1.6 kΩ for 20mA output)
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spi_write(spi, 0x07, 0xA0) # Enable on-chip QRSET (1.6 kΩ for 20mA output)
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spi_write(spi, 0x05, 0x00) # Disable internal IRCML
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spi_write(spi, 0x08, 0x00) # Disable internal QRCML
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spi_write(spi, 0x02, 0xB4) # Enable 2's complement, IFirst: True, IRising: True, DCI_EN: Enabled
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spi_write(spi, 0x14, 0x00)
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spi_write(spi, 0x14, 0x08) # Trigger the retimer to reacquire the clock relationship
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spi_write(spi, 0x14, 0x00)
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register_settings = {
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0x01: 0x40, # Clear EXTREF bit for internal reference,
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0x02: 0xB4, # Enable 2's complement, IFirst: True, IRising: True, DCI_EN: Enabled
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0x0D: 0x00, # Set RREF to 10 kΩ for 1.0V reference
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0x04: 0xA0, # Enable on-chip IRSET (1.6 kΩ for 20mA output)
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0x07: 0xA0, # Enable on-chip QRSET (1.6 kΩ for 20mA output)
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0x05: 0x00, # Disable internal IRCML
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0x08: 0x00, # Disable internal QRCML
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}
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for addr, val in register_settings.items():
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spi_write(spi, addr, val)
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success = verify_registers_vals(spi, register_settings)
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if success:
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# Set manual override output default back to 0V in 2's complement
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set_dac_input_override_value(0x0000)
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return success
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def dac_self_calibration(spi):
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spi_write(spi, 0x12, 0x00) # Reset calibration status
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@ -93,13 +106,14 @@ def dac_self_calibration(spi):
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spi_write(spi, 0x12, 0x00) # Clear calibration bits
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spi_write(spi, 0x0E, 0x30) # Keep CALSELI and CALSELQ set, clear CALCLK
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print("DAC self-calibration completed")
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print("DAC self-calibration completes")
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return True
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def manual_override(enable=True):
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def set_dac_input_override(enable=True):
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reg_contents = read_from_memory(CTRL_ADDR, 1)[0]
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to_write = reg_contents | 0b1 if enable else reg_contents & 0b110
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write_to_memory(CTRL_ADDR, to_write)
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print(f"Set DAC Output Manual Override: {enable}")
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print(f"Enable DAC Input Override: {enable}")
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def power_down_afe(channel, power_down=True):
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assert channel in (0, 1)
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@ -114,7 +128,7 @@ def power_down_afe(channel, power_down=True):
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reg_contents = read_from_memory(CTRL_ADDR, 1)[0]
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print(f"Power Down DAC AFE Ch{channel}: {power_down}")
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def set_dac_output(value):
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def set_dac_input_override_value(value):
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value = min(value, 0x3FFF)
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low_word = value & 0xFF
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high_word = (value >> 8) & 0x3F
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@ -126,19 +140,28 @@ def set_dac_output(value):
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write_to_memory(CH0_LOW_WORD_ADDR, low_word)
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write_to_memory(CH1_HIGH_WORD_ADDR, high_word)
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write_to_memory(CH1_LOW_WORD_ADDR, low_word)
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print(f"DAC output set to: 0x{value:04X}")
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print(f"Set DAC Input Override Value to: 0x{value:04X}")
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def check_clk_relationship(spi):
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# Trigger the retimer to reacquire the clock relationship
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spi_write(spi, 0x14, 0x00)
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spi_write(spi, 0x14, 0x08)
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spi_write(spi, 0x14, 0x00)
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clkmode_reg = spi_read(spi, 0x14)
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print(f"CLKMODE reg: 0x{clkmode_reg:02X}")
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print(f"AD9117 CLKMODE reg: 0x{clkmode_reg:02X}")
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if clkmode_reg & 0b00010000:
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print("Clock relationship is not found")
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print("Ad9117 Clock relationship is established")
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return False
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else:
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print("Clock relationship is found")
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print("Ad9117 Clock relationship is found")
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return True
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def configure_ad9117():
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print()
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print("### Initializing AD9117 Dac")
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success = True
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spi = spidev.SpiDev()
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spi.open(MAIN_DAC_BUS, MAIN_DAC_DEVICE)
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spi.max_speed_hz = 5000
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@ -151,27 +174,30 @@ def configure_ad9117():
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print("Unrecognized DAC version")
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return False
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power_down_afe(0, True)
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power_down_afe(1, True)
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# Disable DAC Output during Initialization
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spi_write(spi, 0x01, 0x46)
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success &= verify_registers_vals(spi, {0x01: 0x46})
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configure_dac(spi)
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check_clk_relationship(spi)
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dac_self_calibration(spi)
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# Enable DAC outputs
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spi_write(spi, 0x01, spi_read(spi, 0x01) & ~((1 << 4) | (1 << 3)))
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success &= configure_dac(spi)
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success &= check_clk_relationship(spi)
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success &= dac_self_calibration(spi)
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power_down_afe(0, False)
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power_down_afe(1, False)
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manual_override(False)
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print("AD9117 configuration completed successfully")
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return True
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if success:
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set_dac_input_override(False)
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# Re-Enable DAC Output
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spi_write(spi, 0x01, 0x40)
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verify_registers_vals(spi, {0x01: 0x40})
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print("AD9117 Dac init completed")
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else:
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print("AD9117 Dac init fails")
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return success
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except Exception as e:
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print(f"Error configuring AD9117: {e}")
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print(f"Error configuring AD9117 Dac: {e}")
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return False
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finally:
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spi.close()
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@ -20,9 +20,30 @@
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from pyfastservo import adc, si5340, dac
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def main():
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si5340.configure_si5340()
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adc.configure_ltc2195()
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dac.configure_ad9117()
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print()
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print("### PL Initialization")
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print()
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# Set output voltage to be 0V after AD9117-2 soft reset
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# DAC starts up in unsigned Data Format. Set DAC to output 0V before Clock is provided to it
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dac.set_dac_input_override_value(0x1FFF)
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dac.set_dac_input_override(True)
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si5340_ok = si5340.configure_si5340()
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adc_ok = adc.configure_ltc2195()
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dac_ok = dac.configure_ad9117()
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if si5340_ok and adc_ok and dac_ok:
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print()
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print("### PL init success")
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print()
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else:
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print()
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print("### Something is wrong with PL init")
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print(f"Si5340 Clock Generator Init Status: {"Success" if si5340_ok else "Failed"}")
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print(f"LTC2195 Adc Init Status: {"Success" if adc_ok else "Failed"}")
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print(f"Ad9117 Dac Init Status: {"Success" if dac_ok else "Failed"}")
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print()
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if __name__ == "__main__":
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main()
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@ -93,6 +93,8 @@ def check_los_status(bus):
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return not xaxb_los
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def configure_si5340():
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print()
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print("### Initializing Si5340 Clock Generator")
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with SMBus(BUS_NO) as bus:
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if not wait_device_ready(bus):
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print("Device not ready. Aborting.")
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@ -271,10 +273,13 @@ def configure_si5340():
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if not pll_locked:
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print("Error: PLL is not locked")
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return False
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elif not xaxb_signal_present:
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print("Error: XA/XB signal is lost")
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||||
return False
|
||||
else:
|
||||
print("Si5340 configuration completed successfully")
|
||||
print("Si5340 init completed")
|
||||
return True
|
||||
|
||||
if __name__ == "__main__":
|
||||
configure_si5340()
|
||||
13
flake.nix
13
flake.nix
@ -431,17 +431,8 @@
|
||||
cp ${fast-servo-gateware}/gateware.bin /lib/firmware/
|
||||
echo gateware.bin > /sys/class/fpga_manager/fpga0/firmware
|
||||
|
||||
# Reset the PL and initialize PL, ADC and DAC clock
|
||||
echo "Configuring Si5340 to generate Clocks"
|
||||
python3 -m pyfastservo.si5340
|
||||
|
||||
# Iniailize ADC
|
||||
echo "Initialize ADC"
|
||||
python3 -m pyfastservo.adc
|
||||
|
||||
# Initialize DAC
|
||||
echo "Initialize DAC"
|
||||
python3 -m pyfastservo.dac
|
||||
# Initialize All PL Peripherals
|
||||
python3 -m pyfastservo.initialize
|
||||
'';
|
||||
})];
|
||||
system = "x86_64-linux";
|
||||
|
||||
Loading…
Reference in New Issue
Block a user