1
0
Fork 0
artiq-zynq/src
Sebastien Bourdeauducq b13da96835 increase CSR bus width to 32 bits
Before:
Minimum interval for sustained TTL output switching ... 1.554e-06

After:
Minimum interval for sustained TTL output switching ... 5.17e-07
2020-07-07 17:22:07 +08:00
..
.cargo cargo: remove outdated runner entry 2020-05-07 13:50:21 +08:00
include fix permissions 2020-07-02 10:28:40 +08:00
libc cc: fixed error and compiled unlzma using cc 2020-07-02 11:41:58 +08:00
libcoreio replace libio with core_io 2020-06-05 17:14:36 +08:00
libdwarf Added libpanic_unwind/dwarf from rustc as libdwarf. 2020-07-02 09:51:47 +08:00
libdyld fix compilation warning 2020-07-02 10:34:43 +08:00
libunwind Backtrace: panic handler with proper backtrace. 2020-07-02 13:12:12 +08:00
llvm_libunwind Libunwind: patched phase1 end of stack detection. 2020-07-02 09:50:53 +08:00
runtime eh_artiq: reduce verbosity 2020-07-07 17:21:28 +08:00
szl use new exception vectors 2020-07-06 21:16:32 +08:00
Cargo.lock update zc706 2020-07-07 12:50:05 +08:00
Cargo.toml Added libpanic_unwind/dwarf from rustc as libdwarf. 2020-07-02 09:51:47 +08:00
Makefile Exception handling: added dependencies to makefile 2020-07-02 10:13:47 +08:00
armv7-none-eabihf.json Exception handling: patched exception handling for ARTIQ. 2020-07-02 10:13:42 +08:00
zc706.py increase CSR bus width to 32 bits 2020-07-07 17:22:07 +08:00