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artiq-zynq
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1.8
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5 Commits
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mwojcik
46b2687d70
RTIO/SYS Clock merge
...
Co-authored-by: mwojcik <mw@m-labs.hk> Co-committed-by: mwojcik <mw@m-labs.hk>
2023-02-17 15:52:43 +08:00
Sebastien Bourdeauducq
ae7ca22db9
dma: fix endianness issues
2020-07-16 17:27:08 +08:00
Sebastien Bourdeauducq
12ba867268
dma: fix and cleanup test
2020-07-13 18:58:08 +08:00
Sebastien Bourdeauducq
5c3c3c26b5
dma: fix inflight_cnt and eop generation
2020-07-13 18:51:55 +08:00
Sebastien Bourdeauducq
ea96cf96d3
dma: add simulation test (WIP)
2020-07-13 12:04:10 +08:00