fsagbuya
/
artiq-zynq
forked from M-Labs/artiq-zynq
1
0
Fork 0
Code Pull Requests Activity

dummy_spi -> pmod_spi

This commit is contained in:
mwojcik 2021-10-14 16:37:13 +08:00
parent 21eb1cab1a
commit 0b27349ec4
1 changed files with 4 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
src/gateware/zc706.py
View File

@ -106,8 +106,8 @@ _ams101_dac = [
)
]
_dummy_spi = [
("dummy_spi", 0,
_pmod_spi = [
("pmod_spi", 0,
# PMOD_1 4-7 pins, same bank as sfp_tx_disable or user_sma_clock
Subsignal("miso", Pins("Y20"), IOStandard("LVCMOS25")),
Subsignal("clk", Pins("AA20"), IOStandard("LVCMOS25")),
@ -467,7 +467,7 @@ class _NIST_CLOCK_RTIO:
platform.add_extension(leds_fmc33)
platform.add_extension(pmod1_33)
platform.add_extension(_ams101_dac)
platform.add_extension(_dummy_spi)
platform.add_extension(_pmod_spi)
rtio_channels = []
@ -516,7 +516,7 @@ class _NIST_CLOCK_RTIO:
phy, ififo_depth=128))
# no SDIO on PL side, dummy SPI placeholder instead
phy = spi2.SPIMaster(platform.request("dummy_spi"))
phy = spi2.SPIMaster(platform.request("pmod_spi"))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4))