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artiq-zynq/runtime/src/main.rs

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Rust
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#![no_std]
#![no_main]
extern crate alloc;
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use core::{cmp, str};
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use libboard_zynq::{
println,
self as zynq, clocks::Clocks, clocks::source::{ClockSource, ArmPll, IoPll},
};
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use libsupport_zynq::{ram, boot};
use libcortex_a9::{mutex::Mutex, sync_channel::{self, sync_channel}};
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mod comms;
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mod pl;
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mod rtio;
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mod kernel;
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fn identifier_read(buf: &mut [u8]) -> &str {
unsafe {
pl::csr::identifier::address_write(0);
let len = pl::csr::identifier::data_read();
let len = cmp::min(len, buf.len() as u8);
for i in 0..len {
pl::csr::identifier::address_write(1 + i);
buf[i as usize] = pl::csr::identifier::data_read();
}
str::from_utf8_unchecked(&buf[..len as usize])
}
}
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static mut STACK_CORE1: [u32; 512] = [0; 512];
static CHANNEL_0TO1: Mutex<Option<sync_channel::Receiver<usize>>> = Mutex::new(None);
static CHANNEL_1TO0: Mutex<Option<sync_channel::Sender<usize>>> = Mutex::new(None);
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#[no_mangle]
pub fn main_core0() {
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println!("ARTIQ runtime starting...");
const CPU_FREQ: u32 = 800_000_000;
ArmPll::setup(2 * CPU_FREQ);
Clocks::set_cpu_freq(CPU_FREQ);
IoPll::setup(1_000_000_000);
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libboard_zynq::stdio::drop_uart(); // reinitialize UART after clocking change
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let mut ddr = zynq::ddr::DdrRam::new();
ram::init_alloc(&mut ddr);
println!("Detected gateware: {}", identifier_read(&mut [0; 64]));
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let core1_stack = unsafe { &mut STACK_CORE1[..] };
let core1 = boot::Core1::start(core1_stack);
let (mut core0_tx, core1_rx) = sync_channel(4);
let (core1_tx, mut core0_rx) = sync_channel(4);
*CHANNEL_0TO1.lock() = Some(core1_rx);
*CHANNEL_1TO0.lock() = Some(core1_tx);
comms::main(core0_tx, core0_rx);
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}
#[no_mangle]
pub fn main_core1() {
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println!("Core1 started");
let mut core1_tx = None;
while core1_tx.is_none() {
core1_tx = CHANNEL_1TO0.lock().take();
}
let mut core1_tx = core1_tx.unwrap();
let mut core1_rx = None;
while core1_rx.is_none() {
core1_rx = CHANNEL_0TO1.lock().take();
}
let mut core1_rx = core1_rx.unwrap();
kernel::main(core1_tx, core1_rx);
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}