Joe's Sayma project plan

Updated 2019-07-03 23:28:38 +08:00

Testing Thermostat v1 with ionpak

Updated 2019-09-13 18:15:10 +08:00

Testing Thermostat v1 with ionpak

Updated 2019-11-14 09:00:13 +08:00

Trivial network-controlled plugs

Updated 2019-12-01 17:04:02 +08:00

Open source laser wavemeter with NO expensive optics and NO machining

Updated 2019-12-12 18:49:33 +08:00

Bare-metal Rust on the Xilinx Zynq ZC706 devkit

Updated 2020-01-06 02:15:21 +08:00

Updated 2020-03-06 11:04:59 +08:00

Next-generation FPGA SoC toolkit

Updated 2020-04-30 16:47:30 +08:00

WinF*VM

Updated 2020-06-30 16:22:55 +08:00

Updated 2020-07-09 15:58:51 +08:00

Updated 2020-07-29 15:18:05 +08:00

Bare-metal Rust on Zynq-7000

Updated 2020-08-12 06:51:53 +08:00

M-Labs website (legacy) - see web2019 repository instead

Updated 2020-08-24 09:58:25 +08:00

A port of [riscv-formal](https://github.com/SymbioticEDA/riscv-formal) to nMigen

Updated 2020-09-21 13:45:43 +08:00

Bare-metal Rust on Zynq-7000

Updated 2020-09-25 15:55:08 +08:00

ARTIQ Zynq-based core device support

Updated 2020-09-25 16:07:47 +08:00

Updated 2020-09-27 14:04:32 +08:00

Simple netboot tool compatible with ARTIQ/MiSoC and SZL bootloaders

Updated 2020-10-15 16:10:44 +08:00

Formally verified ARTIQ RTIO core in nMigen

Updated 2020-11-18 10:49:10 +08:00

Updated 2020-12-08 17:19:14 +08:00