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M-Labs/ artiq
Python 2 8
Updated 2026-02-10 22:12:09 +08:00
srenblad/ artiq
Python 0 0
Updated 2026-02-10 18:52:14 +08:00
M-Labs/ microscope
Python 0 0
Simple FPGA on-chip logic analyzer for Migen
Updated 2026-02-10 15:19:04 +08:00
atse/ artiq
Python 0 0
Updated 2026-02-10 11:16:33 +08:00
bukehu/ assembly
Python 0 0
Repository with instructions and remarks on assembling and testing Sinara hardware. Doesn't pretend to be source of ultimate truth, and can change at any time.
Updated 2026-02-09 18:06:44 +08:00
sinara-hw/ assembly
Python 3 11
Repository with instructions and remarks on assembling and testing Sinara hardware. Doesn't pretend to be source of ultimate truth, and can change at any time.
Updated 2026-02-09 16:59:13 +08:00
atse/ assembly
Python 0 0
Repository with instructions and remarks on assembling and testing Sinara hardware. Doesn't pretend to be source of ultimate truth, and can change at any time.
Updated 2026-02-06 13:03:55 +08:00
fsagbuya/ artiq
Python 0 0
Updated 2026-02-05 17:37:41 +08:00
bukehu/ artiq
Python 0 0
Updated 2026-02-03 18:18:47 +08:00
dpn/ artiq
Python 0 0
Updated 2026-02-02 02:23:16 +08:00
architeuthis/ artiq
Python 0 0
Updated 2026-02-01 04:22:39 +08:00
mwojcik/ artiq
Python 0 0
Updated 2026-01-31 13:27:33 +08:00
M-Labs/ sipyco
Python 0 1
Updated 2026-01-29 20:22:13 +08:00
atse/ urukul-pld
Python 0 0
CPLD/FPGA gateware on Urukul. Forked from https://github.com/quartiq/urukul
Updated 2026-01-28 11:42:33 +08:00
M-Labs/ urukul-pld
Python 0 4
CPLD/FPGA gateware on Urukul. Forked from https://github.com/quartiq/urukul
Updated 2026-01-27 18:11:03 +08:00
occheung/ artiq
Python 0 0
Updated 2026-01-27 13:02:32 +08:00
morgan/ migen
Python 0 0
A Python toolbox for building complex digital hardware
Updated 2026-01-23 12:11:12 +08:00
morgan/ misoc
Python 0 0
The original high performance and small footprint system-on-chip based on Migen™
Updated 2026-01-23 12:11:07 +08:00
M-Labs/ migen
Python 0 3
A Python toolbox for building complex digital hardware
Updated 2026-01-22 18:20:51 +08:00
cklarhor/ migen
Python 0 0
Fork of migen for upstream pull requests and patch staging.
Updated 2026-01-21 20:20:06 +08:00