Bare-metal Rust on Zynq-7000
Updated 2026-02-24 12:03:57 +08:00
Updated 2026-02-23 21:45:40 +08:00
Updated 2026-02-23 16:27:43 +08:00
CPLD/FPGA gateware on Urukul. Forked from https://github.com/quartiq/urukul
Updated 2026-02-23 16:12:49 +08:00
Updated 2026-02-23 14:21:18 +08:00
Sinara datasheets
Updated 2026-02-21 09:39:40 +08:00
Repository with instructions and remarks on assembling and testing Sinara hardware. Doesn't pretend to be source of ultimate truth, and can change at any time.
Updated 2026-02-20 15:46:29 +08:00
Hydra settings and non-flakes packaging code. See https://git.m-labs.hk/m-labs/artiq-extrapkg for new NDSPs and contrib libraries.
Updated 2026-02-16 17:45:43 +08:00
The original high performance and small footprint system-on-chip based on Migen™
Updated 2026-02-16 10:56:14 +08:00
Bare-metal Rust on Zynq-7000
Updated 2026-02-16 09:18:28 +08:00
ARTIQ Zynq-based core device support
Updated 2026-02-16 09:18:21 +08:00
Hydra settings and non-flakes packaging code. See https://git.m-labs.hk/m-labs/artiq-extrapkg for new NDSPs and contrib libraries.
Updated 2026-02-16 09:18:14 +08:00
New ARTIQ compiler, third iteration
Updated 2026-02-16 09:18:03 +08:00
NixOS configuration for pre-installed Linux computers
Updated 2026-02-14 18:24:30 +08:00
NixOS configuration for pre-installed Linux computers
Updated 2026-02-13 18:39:08 +08:00
Updated 2026-02-13 17:04:32 +08:00
Updated 2026-02-13 16:36:01 +08:00
Updated 2026-02-13 13:28:38 +08:00
NixOS configuration for pre-installed Linux computers
Updated 2026-02-12 22:06:52 +08:00
New ARTIQ compiler, third iteration
Updated 2026-02-12 17:47:34 +08:00