ARTIQ Zynq-based core device support
Updated 2025-04-12 18:08:50 +08:00
ARTIQ Zynq-based core device support
Updated 2025-04-11 11:42:34 +08:00
Hydra settings and non-flakes packaging code. See https://git.m-labs.hk/m-labs/artiq-extrapkg for new NDSPs and contrib libraries.
Updated 2025-04-11 11:00:13 +08:00
CPLD/FPGA gateware on Urukul. Forked from https://github.com/quartiq/urukul
Updated 2025-04-11 10:57:28 +08:00
rust-fatfs fork with rs-core_io as dependency instead. No support for chrono.
Updated 2025-04-10 13:39:32 +08:00
rust-fatfs fork with rs-core_io as dependency instead. No support for chrono.
Updated 2025-04-10 13:29:39 +08:00
This is a castellated board designed for fast-servo prototype rev1.0 to replace the malfunctioning Dac analog front end circuitry.
Updated 2025-04-09 12:56:54 +08:00
Updated 2025-03-26 15:42:43 +08:00