ARTIQ Zynq-based core device support
Updated 2025-02-08 12:58:20 +08:00
Updated 2025-02-08 12:58:20 +08:00
Updated 2025-02-08 12:58:20 +08:00
A port of [riscv-formal](https://github.com/SymbioticEDA/riscv-formal) to nMigen
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Trivial network-controlled plugs
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Open source laser wavemeter with NO expensive optics and NO machining
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Testing Thermostat v1 with ionpak
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Bare-metal Rust on the Xilinx Zynq ZC706 devkit
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Firmware for Sinara Fast-Servo based on Not-OS and Linien
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Instrumentation Amplifier Gain Block
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A modified version of compiler-builtins for zynq, with fast memcpy implementation adapted from newlib.
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Bare-metal Rust on Zynq-7000
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WinF*VM
Updated 2025-02-08 12:58:20 +08:00
ARTIQ Zynq-based core device support
Updated 2025-02-08 12:58:20 +08:00
Updated 2025-02-08 12:58:20 +08:00