forked from M-Labs/zynq-rs
ddr: log clock info with debug level
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@ -1,5 +1,5 @@
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use libregister::{RegisterR, RegisterW, RegisterRW};
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use log::{error, info};
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use log::{debug, info, error};
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use crate::{print, println};
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use super::slcr::{self, DdriobVrefSel};
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use super::clocks::{Clocks, source::{DdrPll, ClockSource}};
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@ -41,7 +41,7 @@ impl DdrRam {
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let clocks = Clocks::get();
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let ddr3x_clk_divisor = 2;
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let ddr2x_clk_divisor = 3;
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info!("DDR 3x/2x clocks: {}/{}", clocks.ddr / u32::from(ddr3x_clk_divisor), clocks.ddr / u32::from(ddr2x_clk_divisor));
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debug!("DDR 3x/2x clocks: {}/{}", clocks.ddr / u32::from(ddr3x_clk_divisor), clocks.ddr / u32::from(ddr2x_clk_divisor));
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slcr::RegisterBlock::unlocked(|slcr| {
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slcr.ddr_clk_ctrl.write(
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@ -62,7 +62,7 @@ impl DdrRam {
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.max(1).min(63) as u8;
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let divisor1 = ((DCI_FREQ - 1 + clocks.ddr) / DCI_FREQ / u32::from(divisor0))
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.max(1).min(63) as u8;
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info!("DDR DCI clock: {} Hz", clocks.ddr / u32::from(divisor0) / u32::from(divisor1));
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debug!("DDR DCI clock: {} Hz", clocks.ddr / u32::from(divisor0) / u32::from(divisor1));
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slcr::RegisterBlock::unlocked(|slcr| {
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// Step 1.
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