From c046bbf8a2589e123e91cc3c6bca1f2a150582a5 Mon Sep 17 00:00:00 2001 From: Astro Date: Mon, 21 Oct 2019 22:19:03 +0200 Subject: [PATCH] move slcr, clocks, uart, eth into src/zynq/ --- src/main.rs | 19 ++++++++----------- src/stdio.rs | 2 +- src/{ => zynq}/clocks.rs | 2 +- src/zynq/ddr/mod.rs | 4 ++-- src/{ => zynq}/eth/mod.rs | 4 ++-- src/{ => zynq}/eth/phy/control.rs | 0 src/{ => zynq}/eth/phy/id.rs | 0 src/{ => zynq}/eth/phy/mod.rs | 0 src/{ => zynq}/eth/phy/status.rs | 0 src/{ => zynq}/eth/regs.rs | 0 src/{ => zynq}/eth/rx.rs | 0 src/{ => zynq}/eth/tx.rs | 0 src/zynq/mod.rs | 4 ++++ src/{ => zynq}/slcr.rs | 0 src/{ => zynq}/uart/baud_rate_gen.rs | 0 src/{ => zynq}/uart/mod.rs | 4 ++-- src/{ => zynq}/uart/regs.rs | 0 17 files changed, 20 insertions(+), 19 deletions(-) rename src/{ => zynq}/clocks.rs (99%) rename src/{ => zynq}/eth/mod.rs (99%) rename src/{ => zynq}/eth/phy/control.rs (100%) rename src/{ => zynq}/eth/phy/id.rs (100%) rename src/{ => zynq}/eth/phy/mod.rs (100%) rename src/{ => zynq}/eth/phy/status.rs (100%) rename src/{ => zynq}/eth/regs.rs (100%) rename src/{ => zynq}/eth/rx.rs (100%) rename src/{ => zynq}/eth/tx.rs (100%) rename src/{ => zynq}/slcr.rs (100%) rename src/{ => zynq}/uart/baud_rate_gen.rs (100%) rename src/{ => zynq}/uart/mod.rs (99%) rename src/{ => zynq}/uart/regs.rs (100%) diff --git a/src/main.rs b/src/main.rs index 944192c..8ae3257 100644 --- a/src/main.rs +++ b/src/main.rs @@ -18,11 +18,7 @@ use smoltcp::socket::SocketSet; mod regs; mod cortex_a9; -mod clocks; -mod slcr; -mod uart; mod stdio; -mod eth; mod zynq; use crate::regs::{RegisterR, RegisterW}; @@ -90,7 +86,8 @@ const HWADDR: [u8; 6] = [0, 0x23, 0xde, 0xea, 0xbe, 0xef]; fn main() { println!("Main."); - let clocks = clocks::CpuClocks::get(); + + let clocks = zynq::clocks::CpuClocks::get(); println!("Clocks: {:?}", clocks); println!("CPU speeds: {}/{}/{}/{} MHz", clocks.cpu_6x4x() / 1_000_000, @@ -98,17 +95,17 @@ fn main() { clocks.cpu_2x() / 1_000_000, clocks.cpu_1x() / 1_000_000); - let eth = eth::Eth::default(HWADDR.clone()); + let eth = zynq::eth::Eth::default(HWADDR.clone()); println!("Eth on"); const RX_LEN: usize = 2; - let mut rx_descs: [eth::rx::DescEntry; RX_LEN] = unsafe { uninitialized() }; - let mut rx_buffers = [[0u8; eth::MTU]; RX_LEN]; + let mut rx_descs: [zynq::eth::rx::DescEntry; RX_LEN] = unsafe { uninitialized() }; + let mut rx_buffers = [[0u8; zynq::eth::MTU]; RX_LEN]; // Number of transmission buffers (minimum is two because with // one, duplicate packet transmission occurs) const TX_LEN: usize = 2; - let mut tx_descs: [eth::tx::DescEntry; TX_LEN] = unsafe { uninitialized() }; - let mut tx_buffers = [[0u8; eth::MTU]; TX_LEN]; + let mut tx_descs: [zynq::eth::tx::DescEntry; TX_LEN] = unsafe { uninitialized() }; + let mut tx_buffers = [[0u8; zynq::eth::MTU]; TX_LEN]; let eth = eth.start_rx(&mut rx_descs, &mut rx_buffers); //let mut eth = eth.start_tx(&mut tx_descs, &mut tx_buffers); let mut eth = eth.start_tx( @@ -178,7 +175,7 @@ fn main() { fn panic(info: &core::panic::PanicInfo) -> ! { println!("\nPanic: {}", info); - slcr::RegisterBlock::unlocked(|slcr| slcr.soft_reset()); + zynq::slcr::RegisterBlock::unlocked(|slcr| slcr.soft_reset()); loop {} } diff --git a/src/stdio.rs b/src/stdio.rs index 0860019..ca0900a 100644 --- a/src/stdio.rs +++ b/src/stdio.rs @@ -1,4 +1,4 @@ -use crate::uart::Uart; +use crate::zynq::uart::Uart; const UART_RATE: u32 = 115_200; static mut UART: Option = None; diff --git a/src/clocks.rs b/src/zynq/clocks.rs similarity index 99% rename from src/clocks.rs rename to src/zynq/clocks.rs index a8bb0d5..48da26a 100644 --- a/src/clocks.rs +++ b/src/zynq/clocks.rs @@ -1,5 +1,5 @@ -use crate::slcr; use crate::regs::RegisterR; +use super::slcr; #[cfg(feature = "target_zc706")] const PS_CLK: u32 = 33_333_333; diff --git a/src/zynq/ddr/mod.rs b/src/zynq/ddr/mod.rs index 1d99cec..bac5bcd 100644 --- a/src/zynq/ddr/mod.rs +++ b/src/zynq/ddr/mod.rs @@ -1,6 +1,6 @@ use crate::regs::RegisterW; -use crate::slcr; -use crate::clocks::CpuClocks; +use super::slcr; +use super::clocks::CpuClocks; /// Micron MT41J256M8HX-15E: 667 MHz const DDR_FREQ: u32 = 666_666_666; diff --git a/src/eth/mod.rs b/src/zynq/eth/mod.rs similarity index 99% rename from src/eth/mod.rs rename to src/zynq/eth/mod.rs index 95bf7f9..3c9202e 100644 --- a/src/eth/mod.rs +++ b/src/zynq/eth/mod.rs @@ -1,7 +1,7 @@ use crate::regs::*; -use crate::slcr; use crate::println; -use crate::clocks::CpuClocks; +use super::slcr; +use super::clocks::CpuClocks; pub mod phy; use phy::{Phy, PhyAccess}; diff --git a/src/eth/phy/control.rs b/src/zynq/eth/phy/control.rs similarity index 100% rename from src/eth/phy/control.rs rename to src/zynq/eth/phy/control.rs diff --git a/src/eth/phy/id.rs b/src/zynq/eth/phy/id.rs similarity index 100% rename from src/eth/phy/id.rs rename to src/zynq/eth/phy/id.rs diff --git a/src/eth/phy/mod.rs b/src/zynq/eth/phy/mod.rs similarity index 100% rename from src/eth/phy/mod.rs rename to src/zynq/eth/phy/mod.rs diff --git a/src/eth/phy/status.rs b/src/zynq/eth/phy/status.rs similarity index 100% rename from src/eth/phy/status.rs rename to src/zynq/eth/phy/status.rs diff --git a/src/eth/regs.rs b/src/zynq/eth/regs.rs similarity index 100% rename from src/eth/regs.rs rename to src/zynq/eth/regs.rs diff --git a/src/eth/rx.rs b/src/zynq/eth/rx.rs similarity index 100% rename from src/eth/rx.rs rename to src/zynq/eth/rx.rs diff --git a/src/eth/tx.rs b/src/zynq/eth/tx.rs similarity index 100% rename from src/eth/tx.rs rename to src/zynq/eth/tx.rs diff --git a/src/zynq/mod.rs b/src/zynq/mod.rs index 5a3bfd1..3cd0723 100644 --- a/src/zynq/mod.rs +++ b/src/zynq/mod.rs @@ -1,3 +1,7 @@ +pub mod slcr; +pub mod clocks; +pub mod uart; +pub mod eth; pub mod axi_hp; pub mod axi_gp; pub mod ddr; diff --git a/src/slcr.rs b/src/zynq/slcr.rs similarity index 100% rename from src/slcr.rs rename to src/zynq/slcr.rs diff --git a/src/uart/baud_rate_gen.rs b/src/zynq/uart/baud_rate_gen.rs similarity index 100% rename from src/uart/baud_rate_gen.rs rename to src/zynq/uart/baud_rate_gen.rs diff --git a/src/uart/mod.rs b/src/zynq/uart/mod.rs similarity index 99% rename from src/uart/mod.rs rename to src/zynq/uart/mod.rs index 750597c..973cb48 100644 --- a/src/uart/mod.rs +++ b/src/zynq/uart/mod.rs @@ -1,8 +1,8 @@ use core::fmt; use crate::regs::*; -use crate::slcr; -use crate::clocks::CpuClocks; +use super::slcr; +use super::clocks::CpuClocks; mod regs; mod baud_rate_gen; diff --git a/src/uart/regs.rs b/src/zynq/uart/regs.rs similarity index 100% rename from src/uart/regs.rs rename to src/zynq/uart/regs.rs