forked from M-Labs/zynq-rs
cortex_a9::regs: init U bit for unaligned access
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@ -75,6 +75,6 @@ pub fn dccisw() {
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/// Enable I-Cache and D-Cache
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/// Enable I-Cache and D-Cache
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pub fn sctlr() {
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pub fn sctlr() {
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unsafe {
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unsafe {
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asm!("mcr p15, 0, $0, c1, c0, 0" :: "r" (0x1004) :: "volatile");
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asm!("mcr p15, 0, $0, c1, c0, 0" :: "r" (0x00401004) :: "volatile");
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}
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}
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}
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}
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