forked from M-Labs/zynq-rs
zynq::flash: split into mod transfer
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8a9dde6119
commit
0d1cf04a34
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@ -10,6 +10,8 @@ mod bytes;
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pub use bytes::{BytesTransferExt, BytesTransfer};
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mod spi_flash_register;
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use spi_flash_register::*;
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mod transfer;
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use transfer::Transfer;
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const FLASH_BAUD_RATE: u32 = 50_000_000;
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/// 16 MB
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@ -403,128 +405,4 @@ impl Flash<Manual> {
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{
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Transfer::new(self, args, len)
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}
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}
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pub struct Transfer<'a, Args: Iterator<Item = W>, W: Into<SpiWord>> {
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flash: &'a mut Flash<Manual>,
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args: Args,
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sent: usize,
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received: usize,
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len: usize,
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}
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impl<'a, Args: Iterator<Item = W>, W: Into<SpiWord>> Transfer<'a, Args, W> {
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pub fn new(flash: &'a mut Flash<Manual>, args: Args, len: usize) -> Self {
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flash.regs.config.modify(|_, w| w.pcs(false));
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flash.regs.enable.write(
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regs::Enable::zeroed()
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.spi_en(true)
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);
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let mut xfer = Transfer {
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flash,
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args,
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sent: 0,
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received: 0,
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len,
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};
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xfer.fill_tx_fifo();
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xfer.flash.regs.config.modify(|_, w| w.man_start_com(true));
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xfer
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}
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fn fill_tx_fifo(&mut self) {
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while self.sent < self.len && !self.flash.regs.intr_status.read().tx_fifo_full() {
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let arg = self.args.next()
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.map(|n| n.into())
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.unwrap_or(SpiWord::W32(0));
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match arg {
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SpiWord::W32(w) => {
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// println!("txd0 {:08X}", w);
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unsafe {
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self.flash.regs.txd0.write(w);
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}
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self.sent += 4;
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}
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// Only txd0 can be used without flushing
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_ => {
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if !self.flash.regs.intr_status.read().tx_fifo_not_full() {
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// Flush if neccessary
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self.flash.regs.config.modify(|_, w| w.man_start_com(true));
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self.flash.wait_tx_fifo_flush();
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}
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match arg {
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SpiWord::W8(w) => {
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// println!("txd1 {:02X}", w);
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unsafe {
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self.flash.regs.txd1.write(u32::from(w) << 24);
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}
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self.sent += 1;
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}
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SpiWord::W16(w) => {
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unsafe {
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self.flash.regs.txd2.write(u32::from(w) << 16);
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}
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self.sent += 2;
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}
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SpiWord::W24(w) => {
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unsafe {
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self.flash.regs.txd3.write(w << 8);
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}
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self.sent += 3;
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}
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SpiWord::W32(_) => unreachable!(),
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}
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self.flash.regs.config.modify(|_, w| w.man_start_com(true));
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self.flash.wait_tx_fifo_flush();
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}
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}
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}
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}
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fn can_read(&mut self) -> bool {
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self.flash.regs.intr_status.read().rx_fifo_not_empty()
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}
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fn read(&mut self) -> u32 {
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let rx = self.flash.regs.rx_data.read();
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self.received += 4;
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rx
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}
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}
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impl<'a, Args: Iterator<Item = W>, W: Into<SpiWord>> Drop for Transfer<'a, Args, W> {
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fn drop(&mut self) {
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// Discard remaining rx_data
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while self.can_read() {
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self.read();
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}
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// Stop
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self.flash.regs.enable.write(
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regs::Enable::zeroed()
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.spi_en(false)
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);
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self.flash.regs.config.modify(|_, w| w
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.pcs(true)
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.man_start_com(false)
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);
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}
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}
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impl<'a, Args: Iterator<Item = W>, W: Into<SpiWord>> Iterator for Transfer<'a, Args, W> {
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type Item = u32;
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fn next<'s>(&'s mut self) -> Option<u32> {
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if self.received >= self.len {
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return None;
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}
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self.fill_tx_fifo();
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while !self.can_read() {}
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Some(self.read())
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}
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}
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@ -0,0 +1,127 @@
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use crate::regs::{RegisterR, RegisterW, RegisterRW};
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use super::regs;
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use super::{SpiWord, Flash, Manual};
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pub struct Transfer<'a, Args: Iterator<Item = W>, W: Into<SpiWord>> {
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flash: &'a mut Flash<Manual>,
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args: Args,
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sent: usize,
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received: usize,
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len: usize,
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}
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impl<'a, Args: Iterator<Item = W>, W: Into<SpiWord>> Transfer<'a, Args, W> {
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pub fn new(flash: &'a mut Flash<Manual>, args: Args, len: usize) -> Self {
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flash.regs.config.modify(|_, w| w.pcs(false));
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flash.regs.enable.write(
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regs::Enable::zeroed()
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.spi_en(true)
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);
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let mut xfer = Transfer {
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flash,
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args,
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sent: 0,
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received: 0,
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len,
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};
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xfer.fill_tx_fifo();
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xfer.flash.regs.config.modify(|_, w| w.man_start_com(true));
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xfer
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}
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fn fill_tx_fifo(&mut self) {
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while self.sent < self.len && !self.flash.regs.intr_status.read().tx_fifo_full() {
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let arg = self.args.next()
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.map(|n| n.into())
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.unwrap_or(SpiWord::W32(0));
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match arg {
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SpiWord::W32(w) => {
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// println!("txd0 {:08X}", w);
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unsafe {
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self.flash.regs.txd0.write(w);
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}
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self.sent += 4;
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}
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// Only txd0 can be used without flushing
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_ => {
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if !self.flash.regs.intr_status.read().tx_fifo_not_full() {
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// Flush if necessary
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self.flash.regs.config.modify(|_, w| w.man_start_com(true));
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self.flash.wait_tx_fifo_flush();
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}
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match arg {
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SpiWord::W8(w) => {
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// println!("txd1 {:02X}", w);
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unsafe {
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self.flash.regs.txd1.write(u32::from(w) << 24);
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}
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self.sent += 1;
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}
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SpiWord::W16(w) => {
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unsafe {
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self.flash.regs.txd2.write(u32::from(w) << 16);
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}
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self.sent += 2;
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}
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SpiWord::W24(w) => {
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unsafe {
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self.flash.regs.txd3.write(w << 8);
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}
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self.sent += 3;
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}
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SpiWord::W32(_) => unreachable!(),
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}
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self.flash.regs.config.modify(|_, w| w.man_start_com(true));
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self.flash.wait_tx_fifo_flush();
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}
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}
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}
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}
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fn can_read(&mut self) -> bool {
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self.flash.regs.intr_status.read().rx_fifo_not_empty()
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}
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fn read(&mut self) -> u32 {
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let rx = self.flash.regs.rx_data.read();
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self.received += 4;
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rx
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}
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}
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impl<'a, Args: Iterator<Item = W>, W: Into<SpiWord>> Drop for Transfer<'a, Args, W> {
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fn drop(&mut self) {
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// Discard remaining rx_data
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while self.can_read() {
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self.read();
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}
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// Stop
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self.flash.regs.enable.write(
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regs::Enable::zeroed()
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.spi_en(false)
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);
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self.flash.regs.config.modify(|_, w| w
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.pcs(true)
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.man_start_com(false)
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);
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}
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}
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impl<'a, Args: Iterator<Item = W>, W: Into<SpiWord>> Iterator for Transfer<'a, Args, W> {
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type Item = u32;
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fn next<'s>(&'s mut self) -> Option<u32> {
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if self.received >= self.len {
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return None;
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}
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self.fill_tx_fifo();
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while !self.can_read() {}
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Some(self.read())
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}
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}
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