From 0a3a7776520fa0359fe7dbf40146b9bd22bbc0f8 Mon Sep 17 00:00:00 2001
From: esavkin <es@m-labs.hk>
Date: Fri, 7 Oct 2022 11:04:41 +0800
Subject: [PATCH] Fix soft_rst bit, add reboot function

---
 libboard_zynq/src/slcr.rs | 13 ++++++++++++-
 1 file changed, 12 insertions(+), 1 deletion(-)

diff --git a/libboard_zynq/src/slcr.rs b/libboard_zynq/src/slcr.rs
index e833fd0..f887867 100644
--- a/libboard_zynq/src/slcr.rs
+++ b/libboard_zynq/src/slcr.rs
@@ -587,6 +587,17 @@ register_bit!(a9_cpu_rst_ctrl, a9_clkstop0, 4);
 register_bit!(a9_cpu_rst_ctrl, a9_rst1, 1);
 register_bit!(a9_cpu_rst_ctrl, a9_rst0, 0);
 
+pub fn reboot() {
+    RegisterBlock::unlocked(|slcr| {
+        unsafe {
+            let reboot = slcr.reboot_status.read();
+            slcr.reboot_status.write(reboot & 0xF0FFFFFF);
+            slcr.pss_rst_ctrl.modify(|_, w| w.soft_rst(true));
+        }
+    });
+}
+
+
 #[derive(Clone, Copy, Debug, PartialEq)]
 #[repr(u8)]
 pub enum BootModePins {
@@ -605,7 +616,7 @@ register_bit!(boot_mode, jtag_routing, 3);
 register_bits_typed!(boot_mode, boot_mode_pins, u8, BootModePins, 0, 2);
 
 register!(pss_rst_ctrl, PssRstCtrl, RW, u32);
-register_bit!(pss_rst_ctrl, soft_rst, 1);
+register_bit!(pss_rst_ctrl, soft_rst, 0);
 
 /// Used for MioPin*.io_type
 #[repr(u8)]