forked from M-Labs/zynq-rs
Fix soft_rst bit, add reboot function
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@ -587,6 +587,17 @@ register_bit!(a9_cpu_rst_ctrl, a9_clkstop0, 4);
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register_bit!(a9_cpu_rst_ctrl, a9_rst1, 1);
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register_bit!(a9_cpu_rst_ctrl, a9_rst0, 0);
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pub fn reboot() {
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RegisterBlock::unlocked(|slcr| {
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unsafe {
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let reboot = slcr.reboot_status.read();
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slcr.reboot_status.write(reboot & 0xF0FFFFFF);
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slcr.pss_rst_ctrl.modify(|_, w| w.soft_rst(true));
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}
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});
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}
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#[derive(Clone, Copy, Debug, PartialEq)]
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#[repr(u8)]
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pub enum BootModePins {
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@ -605,7 +616,7 @@ register_bit!(boot_mode, jtag_routing, 3);
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register_bits_typed!(boot_mode, boot_mode_pins, u8, BootModePins, 0, 2);
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register!(pss_rst_ctrl, PssRstCtrl, RW, u32);
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register_bit!(pss_rst_ctrl, soft_rst, 1);
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register_bit!(pss_rst_ctrl, soft_rst, 0);
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/// Used for MioPin*.io_type
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#[repr(u8)]
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