{% extends '_base.html' %}


{% block hero %}

  <div class="container-fluid hero d-flex flex-column justify-content-center">

    <div class="container">

        <div class="row">

          <div class="col-12 text-center">

            <h1>Open tools for open physics.</h1>

            <img src="{{ get_url(path='images/ion@2x.png', cachebust=true) }}" height="12" alt="ion">

          </div>

        </div>

    </div>

  </div>

{% endblock %}


{% block main %}

  <main class="container">

    <div class="row">

      <div class="col-12">

        <div class="card shadow mt-3 mb-3">

          <div class="card-body p-3 p-md-5 card-artiq">

            <div class="col-12 col-md-6 pl-0 pr-0">

              <h5 class="card-title">ARTIQ</h5>

              <p class="card-text pt-3">
                ARTIQ (Advanced Real-Time Infrastructure for Quantum physics) is a leading-edge control system for quantum information experiments, developed in partnership with a growing number of research institutions worldwide.
              </p>

              <p class="card-text pt-3 pb-3">
                The system features a high-level programming language that helps describe complex experiments, which is compiled and executed on dedicated hardware with nanosecond timing resolution and sub-microsecond latency.
              </p>

              <a href="{{ get_url(path='@/experiment-control/artiq.md') }}" class="btn btn-primary btn-lg">Read More</a>
              <a href="{{ get_url(path='@/experiment-control/place-order.md') }}" class="btn btn-primary btn-inversed btn-lg">Order Hardware</a>

            </div>

          </div>

        </div>

      </div>

    </div>


    <div class="row pb-5">

      <div class="col-12">

        <div class="card shadow mt-3 mb-3">

          <div class="card-body p-3 p-md-5 card-gateware">

            <div class="col-12 col-md-6 pl-0 pr-0">

              <h5 class="card-title">Gateware and system-on-chip design</h5>

              <p class="card-text pt-3">
                Traditional gateware design with Verilog and VHDL is well known to be tedious and inefficient. M-Labs have developed Migen, a Python-based HDL and toolbox that addresses many of their issues and makes gateware design more productive.
              </p>

              <p class="card-text pt-3 pb-3">
                Built on Migen, MiSoC provides a high performance, flexible and lightweight solution to build system-on-chips for various applications.
              </p>

              <a href="{{ get_url(path='@/gateware/migen.md') }}" class="btn btn-primary btn-lg">Read More</a>

            </div>

          </div>

        </div>

      </div>

    </div>


    <div class="row pt-5 pb-5">

      <div class="col-12">

        <h3 class="text-center">Contact us</h3>

      </div>

    </div>

  </main>

{% endblock %}