feat(website): Adds page sinara core

content/_index.md

@@ -5,7 +5,7 @@ sort_by = "weight"
 
 Experiment control
  - ARTIQ
- - Sinara
+ - Sinara core
 
 Gateware
  - Migen

content/experiment-control/artiq.md

@@ -85,7 +85,7 @@ Our aim is to provide a control system suitable for the challenges of modern qua
 
 The first ARTIQ core devices used hardware built in-house by physicists. To improve the quality, features and scalability of ARTIQ systems, we have been developing the Sinara device family. It aims at providing turnkey control hardware that is reproducible, open, flexible, modular, well-tested, and well-supported by the ARTIQ control software.
 
-[Learn more](/experiment-control/sinara/)
+[Learn more](/experiment-control/sinara-core/)
 
 {% end %}
 

content/experiment-control/sinara-core.md

@@ -0,0 +1,175 @@
++++
+title = "Sinara core"
+weight = 2
+template = "page-hero.html"
+
+[extra]
+title = "Sinara hardware"
++++
+
+{% textimg(src="images/sinara-hardware@2x.png", alt="", bodyleft=true, customcss="row d-flex align-items-center mb-4 pb-2", shadow=false, md=true) %}
+
+The first ARTIQ core devices used hardware built in-house by physicists (based on a Xilinx KC705 development board with custom FMC cards). To improve the quality, features and scalability of ARTIQ systems, we have been developing the Sinara device family. It aims at providing turnkey control hardware that is reproducible, open, flexible, modular, well-tested, and well-supported by the ARTIQ control software.
+
+The Sinara hardware is in active development, and the latest information is available <a href="https://github.com/sinara-hw" target="_blank" rel="noopener noreferrer">on the wiki of each project's page</a>. Most of the hardware engineering is done at the <a href="http://www.ise.pw.edu.pl/" target="_blank" rel="noopener noreferrer">Institute for Electronics Systems</a> at the Warsaw University of Technology.
+
+Kasli and EEMs can be ordered now. We can deliver a rack-mountable crate that contains all the cards, is fully tested, and is ready to be connected to your experiment and computer network. Contact sales@m-***s.hk with your requirements and we will establish a quote.
+
+{% end %}
+
+
+{% textimg(src="images/kasli@2x.png", alt="sinara crate small", md=true, shadow=false) %}
+
+##### Kasli
+
+One of the main devices in the Sinara family is the Kasli core device. It contains an Artix-7 100T FPGA, DDR3 SDRAM, three SFP connectors, and can control up to 8 daughtercards (Eurocard Extension Module, EEM). The Kasli and its EEMs are installed in one Eurocard 3U chassis. One SFP connector is used for a Gigabit Ethernet connection to your computer network.
+
+<a href="https://github.com/sinara-hw/Kasli/wiki" target="_blank" rel="noopener noreferrer">More information</a>
+
+{% end %}
+
+
+{% textimg(src="images/isolated-ttl@2x.png", alt="", bodyleft=true, customcss="row d-flex align-items-center mb-4 pb-2", shadow=false, md=true) %}
+
+##### Isolated TTL I/O EEMs
+
+For simple TTL signals, we offer I/O cards with 8 channels over BNC or SMA connectors in the EEM form factor. The IOs are divided into two banks of 4, with per-bank ground isolation. The direction (input/output) and termination (high-Z/50R) is selectable on a per-channel basis via I2C or on-board switches. Outputs can supply 5V into 25Ohm, and can tolerate an indefinite short-circuit to ground.
+
+More information: <a href="https://github.com/sinara-hw/DIO_BNC/wiki" target="_blank" rel="noopener noreferrer">BNC card</a> <a href="https://github.com/sinara-hw/DIO_SMA/wiki" target="_blank" rel="noopener noreferrer">SMA card</a>
+
+{% end %}
+
+
+{% textimg(src="images/LVDS@2x.png", alt="sinara crate small", md=true, shadow=false) %}
+
+##### LVDS I/O EEM
+
+For high-density or faster signals, DIO_RJ45 is an extension module supplying 16 LVDS pairs via 4 front-panel RJ45 connectors.
+Each RJ45 supplies 4 LVDS DIOs. The direction (input/output) is individually selectable for each signal via on-board switches. Outputs are intended to drive 100Ohm loads (LVDS is short-circuit protected), inputs are 100Ohm terminated. The connectors dedicate all 8 pins to LVDS signals, ground is on the connector shield so only shielded Ethernet cat 6 shielded cables are allowed.
+
+<a href="https://github.com/sinara-hw/DIO_RJ45/wiki" target="_blank" rel="noopener noreferrer">More information</a>
+
+{% end %}
+
+
+{% textimg(src="images/Banker-TTL-1@2x.png", alt="", bodyleft=true, customcss="row d-flex align-items-center mb-4 pb-2", shadow=false, md=true) %}
+
+##### Banker 128-channel TTL I/O expander
+
+Banker is a versatile 128 TTL GPIO module. It has flexible connectivity and contains a small Lattice iCE40 FPGA, supported by Yosys and IceStorm.
+Interfaces include:
+
+- 8 x 8 channel IDC connectors, compatible with IDC-BNC and future IDC-SMA.
+- 2 x 32 channel VHDCI connectors.
+- 2 downstream EEM connectors that enable daisy-chain connection of several Banker modules.
+- front panel DC Jack and rear side Molex supply connector.
+
+{% end %}
+
+
+{% textimg(src="images/Banker-TTL-2@2x.png", alt="", bodyleft=true, customcss="row d-flex align-items-center mb-4 pb-2", shadow=false, md=true) %}
+
+All outputs can be configured either as 3.3 or 5V. They can drive 50R load when set to 5V. FPGA can is configured from on-board FLASH. FLASH can be updated over I2C or with the on-board SPI connector.
+
+The VHDCI connections can be used to interface with either non-buffered or buffered remote boards that distribute signals to neighboring modules. These modules can be assembled together and placed in COTS enclosures. The enclosures fit onto the low-cost and simple DIN rail standard.
+
+There are several DIN-rail compatible modules for use with Banker. They are interconnected using edge connectors and can be configured as mix of 4 modules of following type:
+
+- 8 channel D-SUB
+- 8 channel BNC
+- 8 channel SMA
+- 8 channel screw terminal
+
+<a href="https://github.com/sinara-hw/Banker/wiki" target="_blank" rel="noopener noreferrer">More information</a>
+
+{% end %}
+
+
+{% textimg(src="images/Urukul-DDS@2x.png", alt="sinara crate small", md=true, shadow=false) %}
+
+##### Urukul DDS card
+
+Urukul is a 4 channel DDS-based frequency synthesizer for the EEM form factor. It provides sub-Hz frequency resolution, controlled phase steps, and accurate output amplitude control. We offer it in two variants, with either the AD9910 or the AD9912 chip.
+
+With the SU-Servo feature of ARTIQ, the AD9910 variant of Urukul (which has fine amplitude control) can be used in combination with the Sampler ADC to form a laser intensity servo. In this application, the Urukul card drives AOMs and photodiodes are connected to Sampler to monitor laser intensities. When ordering your system, specify that you want SU-Servo integrated into the gateware.
+
+In regular mode, various DDS features are supported, including frequency, phase and amplitude control, and AD9910 RAM mode. See the ARTIQ manual for more details.
+
+<a href="https://github.com/sinara-hw/Urukul/wiki" target="_blank" rel="noopener noreferrer">More information</a>
+
+{% end %}
+
+
+{% textimg(src="images/Zotino-DAC@2x.png", alt="", bodyleft=true, customcss="row d-flex align-items-center mb-4 pb-2", shadow=false, md=true) %}
+
+##### Zotino DAC card
+
+Zotino is a 32-channel, 16-bit DAC EEM with an update rate of 1MSPS (divided between the channels). It was designed for low noise and good stability.
+
+Zotino connects the 32 channels to both (a) a HD68 connector on its front panel and (b) to four IDC connectors on the board. Each IDC connection with 8 channels can be broken out to BNC using BNC-IDC.
+
+It is also possible to connect the Zotino using a HD68 cable to an external crate containing BNC-IDC cards.
+
+<a href="https://github.com/sinara-hw/Zotino/wiki" target="_blank" rel="noopener noreferrer">More information</a>
+
+{% end %}
+
+
+{% textimg(src="images/Sampler-ADC@2x.png", alt="sinara crate small", md=true, shadow=false) %}
+
+##### Sampler ADC card
+
+Sampler is an 8-channel, 16-bit ADC EEM with an update rate of up to 1.5MSPS (all channels simultaneously). It has low-noise differential front end with a digitally programmable gain, providing full-scale input ranges between +-10mV (G=1000) and +-10V (G=1).
+
+In SU-Servo mode, Sampler can be used in combination with Urukul to form a laser intensity servo. Otherwise, in regular mode, single sample values can be read out by ARTIQ kernels (due to CPU overhead, the actual sample rate in regular mode is reduced).
+
+<a href="https://github.com/sinara-hw/Sampler/wiki" target="_blank" rel="noopener noreferrer">More information</a>
+
+Note that update rate specification on this page is for the hardware only; ARTIQ kernel and RTIO overhead make the effective sample rate lower. Typically, only with gateware (e.g. SU-Servo) can the maximum bandwidth be achieved. SU-Servo is part of the regular ARTIQ firmware; development of other gateware can be purchased separately.
+
+{% end %}
+
+
+{% textimg(src="images/Grabber-camera-interface@2x.png", alt="", bodyleft=true, customcss="row d-flex align-items-center mb-4 pb-2", shadow=false, md=true) %}
+
+##### Grabber camera interface
+
+Grabber allows the connection of certain scientific (EM)CCD cameras port to the core FPGA. Those cameras have a Camera Link interface.
+
+In the FPGA, frame data streamed through "ROI engines". Each ROI engine gates on one rectangular pixel region and accumulates pixel values for each frame. The ROI engines operate independently and can be overlapping. After the frame, the accumulated value is pushed as an RTIO input event. Regions of interest (ROI) can be configured at runtime, and are defined with the computer.
+
+<a href="https://github.com/sinara-hw/Grabber/wiki" target="_blank" rel="noopener noreferrer">More information</a>
+
+{% end %}
+
+
+{% textimg(src="images/clocker@2x.png", alt="sinara crate small", md=true, shadow=false) %}
+
+##### Clocker
+
+A low-noise clock distribution module that can be used to distribute low jitter clock signal among 3U boards. 2 inputs, 10 outputs including 4 SMAs, frequency up to 1GHz, low jitter <100fs RMS.
+
+<a href="https://github.com/sinara-hw/Clocker/wiki" target="_blank" rel="noopener noreferrer">More information</a>
+
+{% end %}
+
+
+{% layoutlr1() %}
+
+<div class="col-12 col-md-6">
+  <h5>Purchasing Sinara hardware</h5>
+  <p>
+    Kasli and EEMs can be ordered now. We can deliver a rack-mountable crate that contains all the cards, is fully tested, and is ready to be connected to your experiment and computer network.
+    <br><br>
+    Contact sales@m-***s.hk with your requirements and we will establish a quote.
+  </p>
+</div>
+
+<div class="col-12 col-md-6">
+  <h5>Metlino and Sayma</h5>
+  <p>
+    For more demanding experiments, we have been developing the Metlino and Sayma system. One Sayma card includes 8 channels of 2.4GSPS 16-bit DACs and a Kintex Ultrascale FPGA. The FPGA synthesizes waveforms for the DACs and our gateware supports two-tone direct digital synthesis and shaping of the waveform parameters with splines. Multiple Sayma cards can be installed in a MicroTCA chassis together with one Metlino master. Clock synchronization will be supported.
+  </p>
+</div>
+
+{% end %}

content/experiment-control/sinara.md

@@ -1,4 +0,0 @@
-+++
-title = "Sinara"
-weight = 2
-+++

templates/page-hero.html

@@ -19,7 +19,11 @@
 
           <div class="col-12 text-center mt-n0 mt-lg-n5">
 
+            {% if page.extra and page.extra.title %}
+            <h1>{{ page.extra.title }}</h1>
+            {% else %}
             <h1>{{ page.title }}</h1>
+            {% endif %}
 
             <img src="{{ get_url(path='images/ion@2x.png', cachebust=true) }}" width="100" align="ion">
 

templates/shortcodes/layoutlr1.html

@@ -0,0 +1,5 @@
+<div class="row">
+
+  {{ body | safe }}
+
+</div>