refactor(SinaraCore): Reviews layout and md file

content/experiment-control/sinara-core.md

@@ -7,7 +7,8 @@ template = "page.html"
 title = "Sinara hardware"
 +++
 
-{% textimg(src="images/sinara-hardware@2x.png", alt="", bodyleft=true, customcss="row d-flex align-items-center mb-4 pb-2", shadow=false, md=true) %}
+
+{% layout_text_img(src="images/sinara-hardware@2x.png", alt="", textleft=true, shadow=false) %}
 
 The first ARTIQ core devices used hardware built in-house by physicists (based on a Xilinx KC705 development board with custom FMC cards). To improve the quality, features and scalability of ARTIQ systems, we have been developing the Sinara device family. It aims at providing turnkey control hardware that is reproducible, open, flexible, modular, well-tested, and well-supported by the ARTIQ control software.
 
@@ -18,7 +19,8 @@ Kasli and EEMs can be ordered now. We can deliver a rack-mountable crate that co
 {% end %}
 
 
-{% textimg(src="images/kasli@2x.png", alt="sinara crate small", md=true, shadow=false) %}
+
+{% layout_text_img(src="images/kasli@2x.png", alt="", shadow=false) %}
 
 ##### Kasli
 
@@ -29,7 +31,8 @@ One of the main devices in the Sinara family is the Kasli core device. It contai
 {% end %}
 
 
-{% textimg(src="images/isolated-ttl@2x.png", alt="", bodyleft=true, customcss="row d-flex align-items-center mb-4 pb-2", shadow=false, md=true) %}
+
+{% layout_text_img(src="images/isolated-ttl@2x.png", alt="", textleft=true, shadow=false) %}
 
 ##### Isolated TTL I/O EEMs
 
@@ -40,7 +43,8 @@ More information: <a href="https://github.com/sinara-hw/DIO_BNC/wiki" target="_b
 {% end %}
 
 
-{% textimg(src="images/LVDS@2x.png", alt="sinara crate small", md=true, shadow=false) %}
+
+{% layout_text_img(src="images/LVDS@2x.png", alt="", shadow=false) %}
 
 ##### LVDS I/O EEM
 
@@ -52,7 +56,8 @@ Each RJ45 supplies 4 LVDS DIOs. The direction (input/output) is individually sel
 {% end %}
 
 
-{% textimg(src="images/Banker-TTL-1@2x.png", alt="", bodyleft=true, customcss="row d-flex align-items-center mb-4 pb-2", shadow=false, md=true) %}
+
+{% layout_text_img(src="images/Banker-TTL-1@2x.png", alt="", textleft=true, shadow=false) %}
 
 ##### Banker 128-channel TTL I/O expander
 
@@ -67,7 +72,8 @@ Interfaces include:
 {% end %}
 
 
-{% textimg(src="images/Banker-TTL-2@2x.png", alt="", bodyleft=true, customcss="row d-flex align-items-center mb-4 pb-2", shadow=false, md=true) %}
+
+{% layout_text_img(src="images/Banker-TTL-2@2x.png", alt="", textleft=true, shadow=false) %}
 
 All outputs can be configured either as 3.3 or 5V. They can drive 50R load when set to 5V. FPGA can is configured from on-board FLASH. FLASH can be updated over I2C or with the on-board SPI connector.
 
@@ -85,7 +91,8 @@ There are several DIN-rail compatible modules for use with Banker. They are inte
 {% end %}
 
 
-{% textimg(src="images/Urukul-DDS@2x.png", alt="sinara crate small", md=true, shadow=false) %}
+
+{% layout_text_img(src="images/Urukul-DDS@2x.png", alt="", shadow=false) %}
 
 ##### Urukul DDS card
 
@@ -100,7 +107,8 @@ In regular mode, various DDS features are supported, including frequency, phase
 {% end %}
 
 
-{% textimg(src="images/Zotino-DAC@2x.png", alt="", bodyleft=true, customcss="row d-flex align-items-center mb-4 pb-2", shadow=false, md=true) %}
+
+{% layout_text_img(src="images/Zotino-DAC@2x.png", alt="", textleft=true, shadow=false) %}
 
 ##### Zotino DAC card
 
@@ -115,7 +123,8 @@ It is also possible to connect the Zotino using a HD68 cable to an external crat
 {% end %}
 
 
-{% textimg(src="images/Sampler-ADC@2x.png", alt="sinara crate small", md=true, shadow=false) %}
+
+{% layout_text_img(src="images/Sampler-ADC@2x.png", alt="", shadow=false) %}
 
 ##### Sampler ADC card
 
@@ -130,7 +139,8 @@ Note that update rate specification on this page is for the hardware only; ARTIQ
 {% end %}
 
 
-{% textimg(src="images/Grabber-camera-interface@2x.png", alt="", bodyleft=true, customcss="row d-flex align-items-center mb-4 pb-2", shadow=false, md=true) %}
+
+{% layout_text_img(src="images/Grabber-camera-interface@2x.png", alt="", textleft=true, shadow=false) %}
 
 ##### Grabber camera interface
 
@@ -143,7 +153,8 @@ In the FPGA, frame data streamed through "ROI engines". Each ROI engine gates on
 {% end %}
 
 
-{% textimg(src="images/clocker@2x.png", alt="sinara crate small", md=true, shadow=false) %}
+
+{% layout_text_img(src="images/clocker@2x.png", alt="", shadow=false) %}
 
 ##### Clocker
 
@@ -154,17 +165,29 @@ A low-noise clock distribution module that can be used to distribute low jitter
 {% end %}
 
 
-{% layoutsmall(title="Purchasing Sinara hardware") %}
+
-<p class="mb-5">
+{{ layout_separator(separator_title="Purchasing Sinara hardware") }}
-  Kasli and EEMs can be ordered now. We can deliver a rack-mountable crate that contains all the cards, is fully tested, and is ready to be connected to your experiment and computer network.
+
-  <br><br>
+
-  Contact sales@m-***s.hk with your requirements and we will establish a quote.
+
-</p>
+{% layout_centered_content(min_width=true) %}
+
+##### Kasli and EEMs can be ordered now
+
+We can deliver a rack-mountable crate that contains all the cards, is fully tested, and is ready to be connected to your experiment and computer network.
+
+Contact sales@m-***s.hk with your requirements and we will establish a quote.
+
 {% end %}
 
 
-{% layoutsmall(title="Metlino and Sayma") %}
+
-<p>
+{% layout_centered_content(min_width=true) %}
-  For more demanding experiments, we have been developing the Metlino and Sayma system. One Sayma card includes 8 channels of 2.4GSPS 16-bit DACs and a Kintex Ultrascale FPGA. The FPGA synthesizes waveforms for the DACs and our gateware supports two-tone direct digital synthesis and shaping of the waveform parameters with splines. Multiple Sayma cards can be installed in a MicroTCA chassis together with one Metlino master. Clock synchronization will be supported.
+
-</p>
+##### Metlino and Sayma
+
+For more demanding experiments, we have been developing the Metlino and Sayma system. One Sayma card includes 8 channels of 2.4GSPS 16-bit DACs and a Kintex Ultrascale FPGA. The FPGA synthesizes waveforms for the DACs and our gateware supports two-tone direct digital synthesis and shaping of the waveform parameters with splines.
+
+Multiple Sayma cards can be installed in a MicroTCA chassis together with one Metlino master. Clock synchronization will be supported.
+
 {% end %}

templates/shortcodes/layout_centered_content.html

@@ -1,6 +1,6 @@
 <div class="{% if css %}{{ css }}{% else %}row d-flex align-items-center mt-5 mb-5{% endif %}">
 
-  <div class="col-12 text-center">
+  <div class="{% if min_width %}col-12 col-md-8 mx-auto{% else %}col-12{% endif %} text-center">
 
     <p>{{ body | markdown | safe }}</p>