update funding page based on feedback

content/experiment-control/funding.md

@@ -22,10 +22,11 @@ We acknowledge support from our partners below. Please get in touch (sales@m-\*\
 [![log nist](/images/logo_nist.png)](https://www.nist.gov/pml/time-and-frequency-division/ion-storage)
 
 ARTIQ was initiated by the [Ion Storage Group](https://www.nist.gov/pml/time-and-frequency-division/ion-storage) at NIST, who provided valuable technical insight as well as financial support to develop the first version of the ARTIQ software and gateware targeting the KC705 development kit. This included some FPGA SoC libraries such as a SDRAM controller and PHYs, the first two iterations of the ARTIQ runtime including the development of [smoltcp](/software/smoltcp), the RTIO infrastructure and PHYs, the ARTIQ-Python LLVM-based compiler, RTIO DMA, the ARTIQ dashboard and browser, the ARTIQ master, and several controllers. They also supported the more recent ARTIQ port to Zynq, targeting the ZC706 development kit, and enabling ARTIQ-Python kernels to take advantage of the 1GHz CPU in the core device; as well as matrix and trigonometric function support in ARTIQ-Python kernels.
+<small>*Disclaimer: NIST and the United States government are not providing an endorsement of ARTIQ.*</small>
 
-[![logo oxford](/images/logo_oxford.png)](https://www2.physics.ox.ac.uk/)
+[![logo oxford](/images/logo_oxford.png)](https://www2.physics.ox.ac.uk/research/ion-trap-quantum-computing-group)
 
-The [University of Oxford](https://www2.physics.ox.ac.uk/) funded major improvements to the RTIO infrastructure: the Distributed RTIO (DRTIO) system that allows clock synchronization and RTIO command transfer between FPGAs using cost-effective high-speed serial links (e.g. over fiber optics), and changes to the RTIO architecture to improve scalability. They also funded the [SU-Servo](https://m-labs.hk/artiq/manual-beta/core_drivers_reference.html?highlight=suservo#artiq.coredevice.suservo.SUServo) integrated laser intensity servo, firmware development on the Sinara Thermostat, the Kasli v2.0 ARTIQ support, the Fastino ARTIQ support, and parts of the Sinara Phaser gateware and software development.
+The [University of Oxford](https://www2.physics.ox.ac.uk/research/ion-trap-quantum-computing-group) funded major improvements to the RTIO infrastructure: the Distributed RTIO (DRTIO) system that allows clock synchronization and RTIO command transfer between FPGAs using cost-effective high-speed serial links (e.g. over fiber optics), and changes to the RTIO architecture to improve scalability. They also funded the [SU-Servo](https://m-labs.hk/artiq/manual-beta/core_drivers_reference.html?highlight=suservo#artiq.coredevice.suservo.SUServo) integrated laser intensity servo, firmware development on the Sinara Thermostat, the Kasli v2.0 ARTIQ support, the Fastino ARTIQ support, and parts of the Sinara Phaser gateware and software development.
 
 [![logo ise](/images/logo_ise.png)](http://www.ise.pw.edu.pl)
 
@@ -37,9 +38,9 @@ The [University of Oxford](https://www2.physics.ox.ac.uk/) funded major improvem
 
 The [University of Oregon](https://ions.uoregon.edu/) funded a large part of the Sinara Phaser gateware and software development, as well as firmware for the Pounder PDH/phase lock signal generator for Stabilizer.
 
-[![logo jqi](/images/logo_jqi.png)](http://jqi.umd.edu/)
+[![logo arl](/images/logo_arl_devcom.png)](http://brittonlab.umd.edu/)
 
-The [Joint Quantum Institute](http://jqi.umd.edu/), Duke University, and the Army Research Laboratory have funded the development of the SAWG high-throughput digital waveform generator, as well as ARTIQ support for the Sayma and Metlino boards.
+The [Army Research Lab](http://brittonlab.umd.edu/) funded the SAWG high-throughput digital waveform generator, as well as ARTIQ support for the Sayma and Metlino boards.
 
 
 ###### Silver level